CS/COE0447 Computer Organization & Assembly LanguageTopics to cover in Chapter 2MIPS Operations/OperandsMIPS ArithmeticMIPS RegistersGeneral-Purpose RegistersInstruction EncodingMIPS Instruction FormatsR-Format InstructionsR-Format ExampleM I P S Reference Data: CORE INSTRUCTION SETR-Format Instructions (REMINDER)Slide 13R-Format ExampleI-Format InstructionsSlide 16I-Format ExampleSlide 18Slide 19Executing the addi instructionExerciseSlide 22Logic InstructionsLogic Instructions: ExampleAndi and OriLong Immediates (review)Loading a memory addressA programSlide 301CS/COE0447Computer Organization & Assembly LanguageChapter 2 Part 12Topics to cover in Chapter 2•MIPS operations and operands•MIPS registers•Memory view•Instruction encoding•Arithmetic operations•Logic operations•Memory transfer operations3MIPS Operations/Operands•“Operation” (instruction)•“Operand”•MIPS operations–Arithmetic operations (integer/floating-point) (add, sub,…)–Logical operations (and, or,…)–Shift operations (shift a certain number of bits to the left or right)–Compare operations (do something if one operand is less than another,…)–Load/stores to transfer data from/to memory–Branch/jump operations–System control operations/coprocessor operations•MIPS operands–General-purpose registers–Fixed registers, e.g., HI/LO registers–Memory location–Immediate value4MIPS Arithmetic•<op> <rdestination> <rsource1> <rsource2>•All arithmetic instructions have 3 operands–Operand order is fixed: destination first–32 registers (page 2 of green card)•Examples–add $t0, $s0, $s2 # $t0 = $s0 + $s2–sub $s0, $t0, $t1 # $s0 = $t0 – $t1 rd rs rt5MIPS Registersr0r1r2r3r4r5r6r7r8r9r10r11r12r13r14r15r16r17r18r19r20r21r22r23r24r25r26r27r28r29r30r31$zero$at$v0$v1$a0$a1$a2$a3$t0$t1$t2$t3$t4$t5$t6$t7HILOPC$s1$s2$s3$s4$s5$s6$s7$t8$t9$k0$k1$gp$sp$fp$ra$s0General-Purpose Registers Special-Purpose Registers32 bits 32 bits 32 bits6General-Purpose Registers•GPR: all can be used as operands in instructions•Still, conventions and limitations exist to keep GPRs from being used arbitrarily–r0, termed $zero, always has a value “0”–r31, termed $ra (return address), is reserved for subroutine call/return–Etc. (we’ll see otherc conventsion/limitations later)–Register usage and related software conventions are summarized in “application binary interface” (ABI), which is important when writing system software such as an assembler and a compiler7Instruction Encoding•Instructions are encoded in binary numbers–Assembler translates assembly programs into binary numbers–Machine decodes binary numbers to figure out what the instruction is–MIPS has “fixed” 32-bit instruction encoding•MIPS has several instruction formats–R-format: arithmetic instructions–I-format: transfer/branch/immediate format–J-format: jump instruction format–(FI/FR-format: floating-point instruction format)(later chapter)8MIPS Instruction FormatsName Fields Comments6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bitsR-format op rs rt rd shamt funct Arithmetic/logic instruction formatI-format op rs rt address/immediate Transfer, branch, immediate formatJ-format op target address Jump instruction format9R-Format Instructions•Define “fields” of the following number of bits each: 6 + 5 + 5 + 5 + 5 + 6 = 326 5 5 5 65opcode rs rt rd functshamt•For simplicity, each field has a name:For shift instructions:“shift amount”10R-Format Example •MIPS Instruction:add $8,$9,$10Binary number per field representation:Decimal number per field representation:hex representation: decimal representation:On Green Card: Format in column 1, opcodes in column 3(Let’s look and then come back)11M I P S Reference Data: CORE INSTRUCTION SETNAME MNE-MON-ICFOR-MATOPERATION (in Verilog)OPCODE/ FUNCT (hex)Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1)(2) 8hex Branch On Equal beq I if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4hex(1) May cause overflow exception(2) SignExtImm = { 16{immediate[15]}, immediate }(3) ZeroExtImm = { 16{1b’0}, immediate }(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}Later12R-Format Instructions (REMINDER)•Define “fields” of the following number of bits each: 6 + 5 + 5 + 5 + 5 + 6 = 326 5 5 5 65opcode rs rt rd functshamt•For simplicity, each field has a name:13R-Format Example •MIPS Instruction:add $8,$9,$10Binary number per field representation:Decimal number per field representation:Now let’s fill this in14R-Format Example•MIPS Instruction:add $8,$9,$100 9 10 8 320Binary number per field representation:Decimal number per field representation:hex representation: 012A 4020hexdecimal representation: 19,546,144ten000000 01001 01010 01000 10000000000hex15I-Format Instructions•Define “fields” of the following number of bits each: 6 + 5 + 5 + 16 = 326 5 5 16opcode rs rt immediate•For simplicity, each field has a name:Let’s do an example using addi16M I P S Reference Data: CORE INSTRUCTION SETNAME MNE-MON-ICFOR-MATOPERATION (in Verilog)OPCODE/ FUNCT (hex)Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1)(2) 8hex Branch On Equal beq I if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4hex(1) May cause overflow exception(2) SignExtImm = { 16{immediate[15]}, immediate }(3) ZeroExtImm = { 16{1b’0}, immediate }(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}17I-Format Example •MIPS Instruction:addi $8,$9,7Binary number per field representation:Decimal number per field representation:18I-Format Example •MIPS Instruction:addi $8,$9,7Binary number per field representation:Decimal number per field representation:hex representation: 0x21280007 8987001000 01001 01000 0000000000000111hex19M I P S Reference Data: CORE INSTRUCTION SETNAME MNE-MON-ICFOR-MATOPERATION (in Verilog)OPCODE/ FUNCT (hex)Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1)(2) 8hex Branch On Equal beq I if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4hex(1) May cause overflow exception(2) SignExtImm = { 16{immediate[15]}, immediate }(3) ZeroExtImm = { 16{1b’0}, immediate }(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}20addi $8,$9,7Executing the addi instruction$8$9 0x00000023Suppose Immediate = 0x0007 (16 bits; 4 hex
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