CS/COE0447 Computer Organization & Assembly LanguageWe will study the datapath and control using only these instructions [similar ideas apply to others]An Abstract Implementation (fig 5.1)Building Blocks (figs 5.7-5.8)Instruction FetchInstruction ExecutionMemory + R-Instructions (fig 5.10)Instruction Execution, cont’dSlide 9Slide 10Branch Datapath (fig. 5.9)Slide 12Slide 13Datapath so far (fig 5.11)Instruction FormatMore Elaborated Design (fig 5.15)A First Look at Control (fig 5.17)Control Signals OverviewGeneric Control Sequence1CS/COE0447Computer Organization & Assembly LanguageChapter 5Part 12We will study the datapath and control using only these instructions[similar ideas apply to others]•Memory reference instructions–lw (load word) and sw (store word)•Arithmetic-logical instructions–add, sub, and, or, and slt•Control-transfer instructions–beq (branch if equal)–j (unconditional jump)3An Abstract Implementation (fig 5.1)•Combinational logic –ALU, adder•Sequential logic–Register file, instruction memory, data memory4Building Blocks (figs 5.7-5.8)5Instruction FetchInstruction widthis 4 bytes!Instruction memoryhere is read-only!PC keeps the currentmemory addressfrom which instructionis fetched6Instruction Execution•lw (load word) –Fetch instruction lw $t0,-12($t1)–Read a base register $t1–Sign-extend the immediate offset fff4 fffffff4–Add two values to get address X = fffffff4 + $t1–Access data memory with the address M[X]–Store the memory data to the destination register $t07Memory + R-Instructions (fig 5.10) Imm. offsetfor addressLoad datafrom memoryTo be ina register!•E.G: lw $t0,8($t1)8Instruction Execution, cont’d•add–Fetch instruction–Read two source registers–Add two values–Store the result to the destination register9Memory + R-Instructions (fig 5.10) •E.G: add $t2,$t1,$t010Instruction Execution, cont’d•j–Fetch instruction–Take the 26-bit immediate field–Shift left by 2 (to make 28-bit immediate)–Get 4 bits from the current PC and attach to the left of the immediate–Assign the value to PC11Branch Datapath (fig. 5.9)12Memory + R-Instructions (fig 5.10) •E.G: sw $t0,8($t1)13Memory + R-Instructions (fig 5.10) •E.G: add $t0,$t1,$t2; MUX selections are reversed14Datapath so far (fig 5.11)j not consideredso far!15Instruction Format16More Elaborated Design (fig 5.15)ALU control bitsfrom I[5:0]Write register #selection17A First Look at Control (fig 5.17)18Control Signals Overview•RegDst: which instr. field to use for dst. register specifier?–instruction[20:16] vs. instruction[15:11]•ALUSrc: which one to use for ALU src 2?–immediate vs. register read port 2•MemtoReg: is it memory load?•RegWrite: update register?•MemRead: read memory?•MemWrite: write to memory?•Branch: is it a branch?•ALUop: what type of ALU operation?19Generic Control Sequence•For each fetched instruction–(decoding)–Select two registers to read from register file–Select the 2nd ALU input–Select ALU operation–Select if data memory is to be accessed–Select if register file is updated–Select what to assign to
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