LT Spice model parameterization tutorial Perimeter capacitance and CMOS inverter delaySwitching Behavior of CMOS digital logic D. W. ParentE. J. Basham3CMOS Inverter Schematic and Layout34CMOS Inverter Layout and Cross SectionP+N+ N+N+P+A AGND Y VDDPWELLNWELLP+Gate NMOS Gate PMOSS SD DAYEE224 5The delay of a circuit is the measured from the input signal crossing 50% point to the output signal crossing the 50% point.tphltplhoutputinputA majority of the current flows when switchingPower dissipates during switching2DDLoadfVCPA Activity factor~.5Cload all capacitances that are charged or dischargedF frequencyEE224 8When designing Digital circuits MOSFETS can be modeled as a simple RC circuitsDrain CapacitanceThe resistance of the wires to the MOSFET, the resistances of the drain and source and the resistance of the channel.EE224 9The drain capacitance consists of the depletion capacitance between the drain and the body.There is a sidewall depletion capacitance.There is a bottom depletion capacitance.DDWLCapacitance betweenDrain and GateOutput Capacitance modelLDDWSource DrainCurrent FlowLDrainDDWCoutJCoutOVERLAPCoutSIDEWALL1CoutJ Parameter Defined• CJ, is the per area capacitance of the bottom of the PN junction of the source and drain.• CoutJ=CJxWxDDWDDL2CoutSIDEWALLParameter Defined• CoutSIDEWALL, is the per length capacitance of the sidewalls of the PN junction of the source and drain. (Multiply the perimeter by the sidewall capacitance.)• CoutSIDEWALL=2xCJSWx(W+DD)LDrainDDW3CoutOVERLAPParameter Defined• CGD, is the per length capacitance of the overlap of the gate to drain. Due to the Miller Effect this capacitance is multiplied by two.• CoutOVERLAP=2xCGDxWLWDDOVERLAP4EE224 14The delay is found by averaging the resistance over the time spent in linear and saturation and keeping the capacitance constant.time=RCEE224 15Simple CMOS Inverter (spice models added in schematic for this example)EE-166 Class 8 17Usually the load is another CMOS logic gateCMOS gates Drive Other CMOS Gates, and wires that connect one gate to another• We need to convert the WN, WP values of a load into a capacitance (Cexternal) to use in the design equations.LoadDriverWn, Wp of interest18EquationsFitting parameters we wish to find.SiO2N+ N+POLYLLoverlapLoverlapCGDO19Model parameterization added to describe the diffusion dimensions of the source and drain regions.param WP=1000u.param WN 500u.param DD {DD}.param ADP=1*{WP}*{DD}.param ADN=1*{WN}*{DD}.param PDP=2*({WP}+{DD}).param PDN=2*({WN}+{DD})Sweeping the drain width {DD} demonstrates the delay effect on a fixed width and length transistorMeasurement statements for delay.MEAS tfall_out WHEN V(Y)=2.5 cross=3.MEAS trise_out WHEN V(Y)=2.5 cross=4.MEAS trise_in WHEN V(A)=2.5 cross=3.MEAS tfall_in WHEN V(A)=2.5 cross=4.MEAS rise_delay PARAM tfall_out-trise_in.MEAS fall_delay PARAM trise_out-tfall_inAfter the simulation runs, look at the error log (right click on either pane)Right click on spice error log to plot .measure’ddataRight Click on plot pane to add tracesAdd the rise_delay and Fall_delay tracesAs expected the rise delay exceeds the fall delay, and delay increases linearly with increase source/drain perimeter area.The width of Power and Ground lines affect the delay of a circuithttp://www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/ami-c5/t61f-params.txtWhat if the line was aslong as your Project?Current FlowL(di/dt) causes noise and a VDD drop as well.one output pin,@ 25MHzIMAXt=0 t/2tsWhat would happedif we had 64 pins? or
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