EE122 Homework Set 5 Question 1: Please fill out the table below for an NMOS transistor. Answer yes or no for does current flow. Answer cutoff, linear, or saturation for Mode. Choices for the equations are: VT (NMOS) VGS VDS Does Current Flow? Mode ‐1 ‐1 0.1 No Cutoff 0 ‐1 0.1 No Cutoff 1 ‐1 0.1 No Cutoff 2 ‐1 0.1 No Cutoff ‐1 0 0.1 Yes Linear 0 0 0.1 No Cutoff 1 0 0.1 No Cutoff 2 0 0.1 No Cutoff ‐1 0.5 0.1 Yes Linear 0 0.5 0.1 Yes Linear 1 0.5 0.1 No Cutoff 2 0.5 0.1 No Cutoff ‐1 1 0.1 Yes Linear 0 1 0.1 Yes Linear 1 1 0.1 No Cutoff 2 1 0.1 No Cutoff VT (NMOS) VGS VDS Does Current Flow? Mode ‐1 2 0.1 Yes Linear 0 2 0.1 Yes Linear 1 2 0.1 Yes Linear 2 2 0.1 No Cutoff ‐1 ‐1 0.5 No Cutoff 0 ‐1 0.5 No Cutoff 1 ‐1 0.5 No Cutoff 2 ‐1 0.5 No Cutoff ‐1 0 0.5 Yes Linear 0 0 0.5 No Cutoff 1 0 0.5 No Cutoff 2 0 0.5 No Cutoff ‐1 0.5 0.5 Yes Linear 0 0.5 0.5 Yes Saturation 1 0.5 0.5 No Cutoff 2 0.5 0.5 No Cutoff ‐1 1 0.5 Yes Linear 0 1 0.5 Yes Linear 1 1 0.5 No Cutoff 2 1 0.5 No Cutoff ‐1 2 0.5 Yes Linear 0 2 0.5 Yes Linear 1 2 0.5 Yes Linear 2 2 0.5 No Cutoff ‐1 ‐1 2 No Cutoff 0 ‐1 2 No Cutoff VT (NMOS) VGS VDS Does Current Flow? Mode 1 ‐1 2 No Cutoff 2 ‐1 2 No Cutoff ‐1 0 2 Yes Saturation 0 0 2 No Cutoff 1 0 2 No Cutoff 2 0 2 No Cutoff ‐1 0.5 2 Yes Saturation 0 0.5 2 Yes Saturation 1 0.5 2 No Cutoff 2 0.5 2 No Cutoff ‐1 1 2 Yes Saturation 0 1 2 Yes Saturation 1 1 2 No Cutoff 2 1 2 No Cutoff ‐1 2 2 Yes Linear 0 2 2 Yes Saturation 1 2 2 Yes Saturation 2 2 2 No Cutoff Question 2: Please fill out the table below for a PMOS transistor. Answer yes or no for does current flow. Answer cutoff, linear, or saturation for Mode. Write the simplest equation for Model. Choices for the equations are: VT (PMOS) VGS VDS Does Current Flow? Mode 1 1 ‐0.1 No Cutoff 0 1 ‐0.1 No Cutoff ‐1 1 ‐0.1 No Cutoff ‐2 1 ‐0.1 No Cutoff 1 0 ‐0.1 Yes Linear 0 0 ‐0.1 No Cutoff ‐1 0 ‐0.1 No Cutoff ‐2 0 ‐0.1 No Cutoff 1 ‐0.5 ‐0.1 Yes Linear 0 ‐0.5 ‐0.1 Yes Linear ‐1 ‐0.5 ‐0.1 No Cutoff ‐2 ‐0.5 ‐0.1 No Cutoff 1 ‐1 ‐0.1 Yes Linear 0 ‐1 ‐0.1 Yes Linear ‐1 ‐1 ‐0.1 No Cutoff ‐2 ‐1 ‐0.1 No Cutoff 1 ‐2 ‐0.1 Yes Linear 0 ‐2 ‐0.1 Yes Linear ‐1 ‐2 ‐0.1 Yes Linear VT (PMOS) VGS VDS Does Current Flow? Mode ‐2 ‐2 ‐0.1 No Cutoff 1 1 ‐0.5 No Cutoff 0 1 ‐0.5 No Cutoff ‐1 1 ‐0.5 No Cutoff ‐2 1 ‐0.5 No Cutoff 1 0 ‐0.5 Yes Linear 0 0 ‐0.5 No Cutoff ‐1 0 ‐0.5 No Cutoff ‐2 0 ‐0.5 No Cutoff 1 ‐0.5 ‐0.5 Yes Linear 0 ‐0.5 ‐0.5 Yes Saturation‐1 ‐0.5 ‐0.5 No Cutoff ‐2 ‐0.5 ‐0.5 No Cutoff 1 ‐1 ‐0.5 Yes Linear 0 ‐1 ‐0.5 Yes Linear ‐1 ‐1 ‐0.5 No Cutoff ‐2 ‐1 ‐0.5 No Cutoff 1 ‐2 ‐0.5 Yes Linear 0 ‐2 ‐0.5 Yes Linear ‐1 ‐2 ‐0.5 Yes Linear ‐2 ‐2 ‐0.5 No Cutoff 1 1 ‐2 No Cutoff 0 1 ‐2 No Cutoff ‐1 1 ‐2 No Cutoff ‐2 1 ‐2 No Cutoff 1 0 ‐2 Yes SaturationVT (PMOS) VGS VDS Does Current Flow? Mode 0 0 ‐2 No Cutoff ‐1 0 ‐2 No Cutoff ‐2 0 ‐2 No Cutoff 1 ‐0.5 ‐2 Yes Saturation0 ‐0.5 ‐2 Yes Saturation‐1 ‐0.5 ‐2 No Cutoff ‐2 ‐0.5 ‐2 No Cutoff 1 ‐1 ‐2 Yes Saturation0 ‐1 ‐2 Yes Saturation‐1 ‐1 ‐2 No Cutoff ‐2 ‐1 ‐2 No Cutoff 1 ‐2 ‐2 Yes Linear 0 ‐2 ‐2 Yes Saturation‐1 ‐2 ‐2 Yes Saturation‐2 ‐2 ‐2 No Cutoff Question 3: Plot iD vs VDS(0 to 5V) for VGS=0, 1,2 ,3V in LTspice for a simple model NMOS transistor. (kN=constant=1.7x10‐3A/V2, Vt=1V ) Figure 1: Sample ID VDS plot for an NMOS transistor with kN=constant=1.7x10‐3A/V2, Vt=1V, VOV=0, 1.0, 2 , 3V. Figure 2: LTPSPICE Deck for ID VDS plot for an NMOS transistor with kN=constant=1.7x10‐3A/V2, Vt=1V, VGS=0, 1 ,2, 3V. Plot iD vs VDS(0 to ‐5V) for VGS=0, ‐1.0 ,‐2, ‐3V in LTspice for a simple model PMOS transistor. (kP=constant=1x10‐3A/V2, Vt=‐1V ) Figure 3: PMOS plot. Question 4: Plot iD vs VDS(0 to 5V) for VGS=0, 1.25 ,1.5V in LTspice for a simple model NMOS transistor with a finite ro of 10kΩ. (kN=constant=17x10‐3A/V2, Vt=1V ) according to the plot below: Figure 4: Sample plot, ro=10kΩ, kN=1.7x10‐3A/V2, VGS=0, 1.25,1.5V Figure 5: LTSPICE deck ro=10kΩ, kN=1.7x10‐3A/V2, VGS=0, 1.25, 1.5V Question 5: A VDS vs. VGS plot is shown below for a common source amplifier with RD=10kΩ, KN=5mA/V2, VT=.5V, VDD=10V. Mark on the graph where the cutoff, saturation and linear regions are. Where is a likely place to bias (select VGS) the circuit? 0246810120.00 1.00 2.00 3.00 4.00 5.00VDS (V)VGS (V)Bias Here Question 6: A VDS vs. VGS plot is shown below for a common source amplifier with RD=10kΩ, KN=5mA/V2, VT=.5V, VDD=10V. Draw what would happen to the curve if RD=1kΩ, 10kΩ, and 20kΩ. Question 7: Verify that for a common source amplifier with RD=5kΩ, KN=1mA/V2, VT=.5V, VDD=10V, the gain is ‐7.5 if VGS=2V What VGS would we choose if we wanted a gain of ‐5? What would the gain be is VGS=.6Volts? 7.5 What VGS would we choose if we wanted a gain of ‐5? Vs=1.5V What would the gain be if VGS=.6Volts? From the equation AV= ‐.5, which is not gain, but attenuation. For this amplifier the output has to be “small signal” as well. From VGS=.5V to VGS=2.25, the gain changes from zero to ‐8.5 Question 8: What is ID, VD, and VG for KN=1mA/V2, VT=.5V, VDD=10V for the following circuit? Question 9: What is ID, VDS, VGS, And VS for KN=1mA/V2, VT=.5V, VDD=10V for the following circuit?
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