EE122 Homework Set 5 Question 1: Please fill out the table below for an NMOS transistor. Answer yes or no for does current flow. Answer cutoff, linear, or saturation for Mode. Choices for the equations are: VT (NMOS) VGS VDS Does Current Flow? Mode Model ‐1 ‐1 0.1 0 ‐1 0.1 1 ‐1 0.1 2 ‐1 0.1 ‐1 0 0.1 0 0 0.1 1 0 0.1 2 0 0.1 ‐1 0.5 0.1 0 0.5 0.1 1 0.5 0.1 2 0.5 0.1 ‐1 1 0.1 0 1 0.1 1 1 0.1 2 1 0.1 ‐1 2 0.1 0 2 0.1 1 2 0.1 2 2 0.1 ‐1 ‐1 0.5 0 ‐1 0.5 1 ‐1 0.5 2 ‐1 0.5 ‐1 0 0.5 0 0 0.5 1 0 0.5 2 0 0.5 VT (NMOS) VGS VDS Does Current Flow? Mode Model ‐1 0.5 0.5 0 0.5 0.5 1 0.5 0.5 2 0.5 0.5 ‐1 1 0.5 0 1 0.5 1 1 0.5 2 1 0.5 ‐1 2 0.5 0 2 0.5 1 2 0.5 2 2 0.5 ‐1 ‐1 2 0 ‐1 2 1 ‐1 2 2 ‐1 2 ‐1 0 2 0 0 2 1 0 2 2 0 2 ‐1 0.5 2 0 0.5 2 1 0.5 2 2 0.5 2 ‐1 1 2 0 1 2 1 1 2 2 1 2 ‐1 2 2 0 2 2 1 2 2 2 2 2 Question 2: Please fill out the table below for a PMOS transistor. Answer yes or no for does current flow. Answer cutoff, linear, or saturation for Mode. Write the simplest equation for Model. Choices for the equations are: (1) (2) (3) VT (PMOS) VGS VDS Does Current Flow? Mode Model 1 1 ‐0.1 0 1 ‐0.1 ‐1 1 ‐0.1 ‐2 1 ‐0.1 1 0 ‐0.1 0 0 ‐0.1 ‐1 0 ‐0.1 ‐2 0 ‐0.1 1 ‐0.5 ‐0.1 0 ‐0.5 ‐0.1 ‐1 ‐0.5 ‐0.1 ‐2 ‐0.5 ‐0.1 1 ‐1 ‐0.1 0 ‐1 ‐0.1 ‐1 ‐1 ‐0.1 ‐2 ‐1 ‐0.1 1 ‐2 ‐0.1 0 ‐2 ‐0.1 ‐1 ‐2 ‐0.1 ‐2 ‐2 ‐0.1 1 1 ‐0.5 0 1 ‐0.5 ‐1 1 ‐0.5 ‐2 1 ‐0.5 1 0 ‐0.5 0 0 ‐0.5 ‐1 0 ‐0.5 ‐2 0 ‐0.5 1 ‐0.5 ‐0.5 0 ‐0.5 ‐0.5 ‐1 ‐0.5 ‐0.5 VT (PMOS) VGS VDS Does Current Flow? Mode Model ‐2 ‐0.5 ‐0.5 1 ‐1 ‐0.5 0 ‐1 ‐0.5 ‐1 ‐1 ‐0.5 ‐2 ‐1 ‐0.5 1 ‐2 ‐0.5 0 ‐2 ‐0.5 ‐1 ‐2 ‐0.5 ‐2 ‐2 ‐0.5 1 1 ‐2 0 1 ‐2 ‐1 1 ‐2 ‐2 1 ‐2 1 0 ‐2 0 0 ‐2 ‐1 0 ‐2 ‐2 0 ‐2 1 ‐0.5 ‐2 0 ‐0.5 ‐2 ‐1 ‐0.5 ‐2 ‐2 ‐0.5 ‐2 1 ‐1 ‐2 0 ‐1 ‐2 ‐1 ‐1 ‐2 ‐2 ‐1 ‐2 1 ‐2 ‐2 0 ‐2 ‐2 ‐1 ‐2 ‐2 ‐2 ‐2 ‐2 Question 3: Plot iD vs VDS(0 to 5V) for VGS=0, 1,2 ,3V in LTspice for a simple model NMOS transistor. (kN=constant=1.7x10‐3A/V2, Vt=1V ) Figure 1: Sample ID VDS plot for an NMOS transistor with kN=constant=1.7x10‐3A/V2, Vt=1V, VOV=0, 1.0, 2 , 3V. Figure 2: LTPSPICE Deck for ID VDS plot for an NMOS transistor with kN=constant=1.7x10‐3A/V2, Vt=1V, VGS=0, 1 ,2, 3V. Plot iD vs VDS(0 to ‐5V) for VGS=0, ‐1.0 ,‐2, ‐3V in LTspice for a simple model PMOS transistor. (kP=constant=1x10‐3A/V2, Vt=‐1V ) Question 4: Plot iD vs VDS(0 to 5V) for Vov=0, 1.25 ,1.5V in LTspice for a simple model NMOS transistor with a finite ro of 10kΩ. (kN=constant=17x10‐3A/V2, Vt=1V ) according to the plot below: Figure 3: Sample plot, ro=10kΩ, kN=1.7x10‐3A/V2, VGS=0, 1, 2, 3V Figure 4: LTSPICE deck ro=10kΩ, kN=1.7x10‐3A/V2, VGS=0, 1,2, and 3V Question 5: A VDS vs. VGS plot is shown below for a common source amplifier with RD=10kΩ, KN=5mA/V2, VT=.5V, VDD=10V. Mark on the graph where the cutoff, saturation and linear regions are. Where is a likely place to bias (select VGS) the circuit? 0246810120.00 1.00 2.00 3.00 4.00 5.00VDS (V)VGS (V)Question 6: A VDS vs. VGS plot is shown below for a common source amplifier with RD=10kΩ, KN=5mA/V2, VT=.5V, VDD=10V. Draw what would happen to the curve if RD=1kΩ, and 20kΩ. 0246810120.00 1.00 2.00 3.00 4.00 5.00VDS (V)VGS (V)Question 7: Verify that for a common source amplifier with RD=5kΩ, KN=1mA/V2, VT=.5V, VDD=10V, the gain is ‐7.5 if VGS=2V What VGS would we choose if we wanted a gain of ‐5? What would the gain be is VGS=.6Volts? Question 8: What is ID, VD, and VG for KN=1mA/V2, VT=.5V, VDD=10V for the following circuit? Question 9: What is ID, VDS, VGS, And VS for KN=1mA/V2, VT=.5V, VDD=10V for the following circuit?
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