IntroductionSPART DesignSPART Functional DescriptionSPART StructureBus InterfaceBaud Rate GeneratorMore InformationHardware TestbenchHardware HarnessImplementation InformationLab WorkReportSPARTA Special Purpose Asynchronous Receiver/TransmitterIntroductionIn this miniproject you are to implement a Special Purpose Asynchronous Receiver/Transmitter (SPART). The SPART can be integrated into the processor of your final project to serve as the serial I/O interface between the processor and serial I/O port on the lab workstations. Using the Hypertermial Accessory program, this will permit you to input characters from the keyboard and to output characters to the screen on the lab workstations. The objectives of this miniproject are to:- Familiarize you with design in the ECE 554 XUP Virtex-2 Pro Board environment- Practice the use of an HDL in design- Generate a useful design for your final project- Acquire an initial experience in efficiently and effectively performing a design as a teamSPART DesignSPART Functional DescriptionThis section specifies the subsystem to be designed. In order to classify the description, some terminology is necessary. The term output or write are used when the processor is sending information to the SPART. The term transmit is used when the SPART is transmitting data to the serial I/O port on theworkstation. Conversely, the terms input or read are used when the processor is retrieving information from the SPART. Finally, the term receive is used when the SPART is receiving data from the serial I/O port on the workstation.IOADDR SPART Register00Transmit Buffer (IOR/W = 0); Receive Buffer (IOR/W = 1)01Status Register (IOR/W = 1)10DB(Low) Division Buffer11DB(High) Division BufferTable 1: Address Mappings1Figure 1: SPART EnvironmentA top level diagram of the SPART and its environment is shown in Figure 1. The FPGA interfaces with a chip on the board which generates appropriate voltage levels for the RS232 interface. The TxD pin transmits serial data from the FPGA and RxD receives serial data.The SPART and Processor driver share many interconnections in order to control the reception and transmission of data. On the left, the SPART interfaces to an 8-bit, 3-state bidirectional bus, DATABUS[7:0]. This bus is used to transfer data and control information between the Processor and the SPART. In addition, there is a 2-bit address bus, IOADDR[1:0] which is used to select the particular register that interacts with the DATABUS during an I/O operation. The IOR/W signal determines the direction of data transfer between the Processor and SPART. For a Read (IOR/W=1), data is transferred from the SPART to the Processor and for a Write (IOR/W=0), data is transferred from the processor to theSPART. IOCS and IOR/W are crucial signals in properly controlling the three-state buffer on DATABUS within the SPART. Receive Data Available (RDA), is a status signal which indicates that a byte of data has been received and is ready to be read from the SPART to the Processor. When the read operation is performed, RDA is reset. Transmit Buffer Ready (TBR) is a status signal which indicates that the transmit buffer in the SPART is ready to accept a byte for transmission. When a write operation is performed and the SPART is not ready for more transmission data, TBR is reset. The SPART is fully synchronous with the clock signal CLK; this implies that transfers between the Processor and SPART can be controlled by applying IOCS, IOR/W, IOADDR, and DATABUS (in the case of a write operation) for a single clock cycle and capturing the transferred data on the next positive clock edge. The received data on RxD, however, is asynchronous with respect to CLK. Also, the serial I/O port on the workstation which receives the transmitted data from TxD has no access to CLK. This interface thus constitutes the “A” for “Asynchronous” in SPART and requires an understanding of RS-232 signal timing and (re)synchronization.2SPART StructureA block diagram of the SPART is given in Figure 2. Each subsystem is briefly described in this section.Figure 2: SPART Block DiagramBus InterfaceThe Bus Interface contains the 3-state drives which attach the SPART to the DATABUS. In addition, it contains the multiplexer which selects the Receive Buffer or the Status Register. The Status Register consists of RDA and TBR in positions 0 and 1, respectively. The Status Register is not actually a register, but just connections from RDA and TBR which are stored at their respective sources. The remaining six bits connected to the multiplexer for the Status Register are zeros. Note that RDA and TBR are provided both as direct signals to the Processor and as part of the Status Register content accessible by the Processor via the DATABUS. If interrupt-based I/O is used for the SPART, then the direct signals can be used as inputs to the interrupt system. If program-based I/O is used, then the Status Register content (RDA, TBR) can be accessed by the program using an I/O read operation on the Status Register to determine if an I/O data operation is needed. In either case, RDA and TBR can be used as part of a “handshake” between the processor and the SPART during I/O transactions.In addition to the above datapath constructs, the Bus Interface also contains combinational control logic for the above. In particular, it uses IOCS and IOR/W to make sure that the 3-state drivers are never turned on in conflict with other drivers on DATABUS.3Baud Rate GeneratorThe BAUD Rate Generator (BRG) produces an enabling signal or signals for controlling the transmitter and the receiver. In traditional UART designs, transmitter and receiver clocks, which typically are the same frequency, are used to perform the necessary timing for controlling the BAUD rate of the transmitted serial information and for controlling the sampling of received information. Since we have noseparate clock source, we cannot use this approach, but must instead depend upon the BRG to produce enable signals for these purposes instead of separate clocks. The reason for producing an enable signal instead of a clock is to avoid the problem of having multiple clock domains. The enable signal is produced by a down counter and decoder circuit to perform divisions of the frequency of CLK. Note that in Verilog, an enable is not used as a clock, but as a condition for performing or not performing actions:always@(posedge clk) if (enable) ...