CoverTOCAbout the FPGA ToolFeatures and BenefitsMethodologyDesignWizard FlowPush-Button FlowPerformance (Constraint-Driven) FlowScript-Based FlowHierarchical (Multiple-Device) FlowUsing the Graphical User InterfaceAbout the Tip BarAbout the Output WindowUsing the Mouse Buttons and Context MenusGetting Help from the GUIUsing the ShellFPGA Scripting Tool (FST) Command OverviewCommand GroupsUsing the Man PagesUsing Memory Elements With Lucent DevicesMixing HDL and Netlist InputCreating a Finite State Machine (FSM)Creating an FSM Using a VHDL TemplateCreating an FSM Using a Verilog TemplateUsing Encrypted Intellectual PropertyCreating a ProjectSpecifying Design Source FilesDebugging Design Source FilesElaborating a DesignIdentifying the Top-Level DesignCreating the ImplementationImporting ConstraintsEntering Constraints, Attributes, and ControlsEditing Table CellsSetting Multicycle Timing ConstraintsSetting General Synthesis OptionsSetting Project Synthesis OptionsUpdating and Force-Updating a Project After Incremental ChangesViewing a Schematic of an RTL (Generic) DesignViewing a Schematic of an Optimized (Mapped) DesignAnalyzing TimingViewing Timing Results Graphically Using TimeTrackerGenerating a NetlistGenerating a ReportGenerating a Project DatabaseUsing Quartus IIAbout the ASCII Constraint File FormatHeader InformationClock ConstraintsObject GroupsPath ConstraintsPort ConstraintsModule ConstraintsRegister ConstraintsVendor OptionsExporting an ASCII Constraint FileImporting an ASCII Constraint FileIntroductionProject VariablesFST CommandsConstraints CommandsReports CommandsBrowsing Objects CommandsTiming CommandsSource Design Management CommandsTarget Management CommandsLogical Library Management CommandsChip Management CommandsSource File Management CommandsProject Management CommandsBuilt-In Tcl CommandsOther CommandsIndexABCDEFGHIKLMNOPRSTUVXComments?E-mail your comments about Synopsys documentation to [email protected] Express™User GuideVersion 2001.08-FE3.6.1, August 2001iiCopyright Notice and Proprietary InformationCopyright  2001 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.Right to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. 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IntroductionAbout the FPGA Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32. Choosing a Design FlowDesignWizard Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2Push-Button Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3Performance (Constraint-Driven) Flow . . . . . . . . . . . . . . . . . . . . .