Table of Contents 1 Introduction 4 1.1 System Overview 4 1.2 RISC-E Pipeline Summary 5 1.3 Comparison with the Original MIPS RISC Architecture 6 1.4 The FPGA, Prototyping Board, and Design Process 6 1.5 Levels of Abstraction 7 1.6 A Note About Fonts 9 2 ISA 10 2.1 Arithmetic Instructions 11 2.2 Logical Instructions 13 2.3 Shift Instructions 15 2.4 No-Operation 17 2.5 Immediate Instructions 18 2.6 Memory Instructions 19 2.7 Stack Instructions 22 2.8 Jump Instructions 24 2.9 Branch Instructions 25 2.10 Data Dependencies 27 3 Hardware 29 3.1 Processor Overview 29 3.1.1 Program Counter 30 3.1.2 Arithmetic/Logical Unit (ALU) 32 3.1.3 Register File (RF) 33 3.1.4 Pipeline Registers 36 3.1.4.1 FD Register 37 3.1.4.2 DX Register 38 3.1.4.3 XM Register 39 3.1.4.4 MW Register 40 3.1.5 Control Generator 41 3.1.6 Hazard Detection Unit 43 3.1.6.1 Structural Hazards 44 3.1.6.2 Data Hazards 45 3.1.6.2.1 Data Forwarding / Bypassing 45 3.1.6.3 Pipeline Stalling 46 3.1.6.4 Control / Branch Hazard 47 3.2 Memory Interface Unit (MIU) 49 3.2.1 Synchronization 51 3.3 VGA Unit 52 3.3.1 Overview 52 3.3.2 Signal Specifications 52 3.3.3 Operation 53 3.3.3.1 RAMDAC Initialization 53 3.3.3.2 Data and Synchronization Generation 533.3.3.3 Pixel Manipulation 54 3.3.3.4 Character Generation 55 3.3.3.4.1 Decoder Lookup ROM 56 3.4 Keyboard Controller 57 3.4.1 Keyboard-to-Controller Communication 58 3.4.2 Controller-to-Keyboard Communication 59 3.4.3 Structure of the Keyboard Controller 60 3.5 RISC-E Hardware Summary and Execution Trace 63 4 Software 71 4.1 Development Software 71 4.1.1 Sim 71 4.1.1.1 Syntax of Sim 72 4.1.1.2 Programming with Sim 73 4.1.1.3 Instructions in Sim 74 4.1.1.4 Registers and Arguments 75 4.1.1.5 Labels 76 4.1.1.6 Comments and Whitespace 76 4.1.1.7 Reserved word STOP 76 4.1.1.8 I/O (Input / Output) 77 4.1.1.9 bmpgen for Viewing Pixel Output 80 4.1.1.10 Files 82 4.1.2 AssemblerT 83 4.1.3 Assembly Text Generator 90 4.1.4 Bitmap to XES-16 Converter 92 4.2 Board Software 93 4.2.1 Demonstration Programs 93 4.2.1.1 Shell 93 4.2.1.1.1 Interactive Mode 93 4.2.1.1.2 Dispatch Mode 94 4.2.1.2 Etch-a-Sketch 95 4.2.1.3 Fire 96 4.2.1.4 PONG! 96 4.2.1.4.1 Overview 96 4.2.1.4.2 Development 97 4.2.1.5 Snake 98 4.2.2 Test Programs 101 4.2.2.1 AAA 101 4.2.2.2 Alpha 101 4.2.2.3 Echo 102 4.2.3 Stdlib.asm 102 5 Results 103 5.1 Team Member Contributions 104- 4 - 1 Introduction 1.1 System Overview The RISC-E Microprocessor is a special-purpose MIPS RISC-based system, optimized for character-based (console-style) input/output. RISC-E features a 32-bit five-stage pipelined datapath capable of integer instructions, a complete VGA (Video Graphics Array) interface, and a PS/2 Keyboard Controller. RISC-E also includes some additional instructions designed to streamline assembly-level programming (see 2 ISA). Instruction pipelining and a high-performance ALU ensure short average execution times and high instruction throughput—nonetheless, the programmer will find assembly-level programming in RISC-E to be a straightforward process—with helpful optimizations for I/O and instructions designed to simplify development. Additionally, simulation and assembling tools for the RISC-E architecture speed the testing and debugging process, and a helpful library of function calls reduces repetitive coding. An on-board Memory Interface Unit (MIU) allows the 32-bit RISC-E Microprocessor to operate on a 16-bit development board without any visible changes to processor layout or instruction execution. The core of the RISC-E processor is a 32-bit machine—no design modifications were required to implement the design on the prototyping hardware. As a result, the RISC-E Microprocessor is capable of addressing 218 unique addresses in memory—each of which has width 32 bits—while the underlying hardware has width 16 bits. The peripheral devices have also been designed specifically to simplify character I/O. The PS/2 Keyboard controller interfaces directly with the RISC-E Microprocessor through a dedicated register—nearly invisible to system operation, and easy to access. The controller translates keyboard scan codes to ASCII characters in hardware, greatly simplifying keyboard input. Similarly the VGA Unit accepts ASCII input and prints the corresponding character to the screen without requiring individual pixel manipulation by the processor to produce characters. The result is a very efficient method to perform character-based I/O—without unnecessary software overhead. The register file of the RISC-E Microprocessor includes 32 registers, 28 of which are general-purpose. Any of these registers may be used in a given instruction—there are no restrictions on when a particular register in the file may be addressed. Special purpose registers include a zero register (R0 always fixed at zero), a dedicated I/O register (R29), a stack pointer (R30), and a return-address register (R31). The ALU (Arithmetic/Logical Unit) supports the most common integer operations—add, subtract, shift, rotate, and multiply in a single cycle, allowing for efficient computation and high throughput. Data forwarding and pipeline hazard detection allows the ALU’s utilization to approach 100%. RISC-E’s load/store memory architecture is straightforward, but versatile, allowing the programmer to read or write to any addressable memory location by providing a base- 5 - address, an offset and a destination register (for a load word instruction, lw) or a data source register (for a store word instruction, sw). Additionally, push/pop instructions and a self-incrementing/decrementing stack pointer greatly improve the programmer’s ability to employ functions and procedures, even recursion, while maintaining a system stack pointer without mistake-prone arithmetic operations. It is important to note that RISC-E does not include instruction or data caches. In fact, this is not a disadvantage—the memory system is capable of operating at the same speed as the microprocessor itself (in truth, memory