ECE 554 – Digital Engineering Laboratory FPGA Design Tutorial Version 4.1 – Fall 2003 Matt King, Surin Kittitornkun and Charles R. Kime Table of Contents 1. Introduction and Preparation………………………………………………………… 2 2. Design Entry…………………………………………………………………………. 3 3. Functional Simulation………………………………………………………………... 7 4. Design Synthesis……………………………………………………………………... 11 5. Post-Synthesis Simulation…………………………………………………………… 15 6. Design Implementation………………………………………………………………. 16 7. Timing (Post Implementation) Simulation…………………………………………… 21 8. Conclusion……………………………………………………………………………. 24 9. References…………………………………………………………………………….. 25 Appendixes A. HDL Design Wizard and Language Assistant…………………………………………. 26 B. Syntax checking for HDL Synthesis vs. HDL Simulation……………………………... 29 C. Incremental Design Synthesis………………………………………………………….. 30 Changes to V.3.0 - Post-synthesis simulation has been added. - Flow diagrams have been added. Changes to V.3.1 - Design Synthesis: Adding Verilog cores (*.v) to FPGA Express instead of EDIF (*.edn) - This can solve some unexpected synthesis problems when the design is more complex and help identify the Warnings in FPGA Express. Changes to V.4 - Updated for Xilinx Foundation 4.2i and Modelsim 5.6d Changes to V.4.1 - Updated for Modelsim 5.7e21. Introductions and Preparation The FPGA design flow can be divided into the following stages: 1. Design Entry a) Performing HDL coding for synthesis as the target (Xilinx HDL Editor) b) Using Cores (Xilinx Core Generator) 2. Functional Simulation of synthesizable HDL code (MTI ModelSim) 3. Design Synthesis (FPGA Express) 4. Design Implementation (Xilinx Design Manager) 5. Timing (Post Implementation) Simulation (MTI ModelSim) This design flow is based on the assumption that the student: 1. Is familiar with HDL coding using either Verilog HDL or VHDL. See Appendix A: Design Wizard and Language Assistant, and 2. Recognizes the difference between HDL coding for synthesis and for simulation. See Appendix B: Syntax checking for HDL Synthesis vs. HDL Simulation. The final ECE 554 project usually contains a big/complex subsystem, which takes a long time to synthesize (>10 min.) and is unchanged or infrequently changed during the system debugging loop. See Appendix C: Incremental Design Synthesis for further details. Preparation - Log on a Windows workstation (in 3628 Engineering Hall only). - Create “I:\xilinx\tutorial\mac” and “I:\xilinx\tutorial\cores” directories - Copy files from http://www.cae.wisc.edu/~ece554/s03/mac and http://www.cae.wisc.edu/~ece554/s03/core respectively. File name Detail mltring.v The top most file contains the “mltring” module and other interfaces. mac.v The top-level file contains “mac_test” module. (MAC = Multiply-ACcumulate) mltring.ucf User constraint file contains port names and their corresponding pin location assignments. force.do Script file to simulate “mac.v” in ModelSim (functional) timing_force.do Script file to simulate “mltring.v” in ModelSim (timing) mult_4x4.* 4-by-4 bit multiplier core: .v for functional simulation, .edn for netlist reg8b.* 8-bit register core: .v for functional simulation, .edn for netlist3 2. Design Entry Since you’re required to do the projects in HDL (hardware description language) only, the HDL editor is provided. All the keywords are highlighted depending on the file extension either “*.vhd” for VHDL or “*.v” for Verilog HDL. • Using HDL Editor  Open the HDL Editor by double clicking on the HDE icon on the desktop.  Open the top-level file: “mac.v” in “I:\xilinx\tutorial\mac” and try to understand the structure of the multiply-accumulator. You must be able to draw a simple diagram with some useful details described by this HDL code and show it to the instructor.  Open “mltring.v” in the same directory and find where the “mac_test” module is instantiated at a specific line number. Show this to the instructor. • Using Cores from Core Generator The pre-designed functional units such as adder/subtractor, multiplier, divider, etc. are available in such a way that they can be customized for a particular use. These functional units are called “cores.” They can be customized and generated using “Xilinx Core Generator” which can be used in the following procedure. • Launch Core Generator: Design EntryVerilog CodingHDE.exeCoresCore generatorFunctional Sim.ModelSimVerilog SynthesisFPGA ExpressImplementationDesign Mgr.Post-Syn. Sim.ModelSimTiming Sim.ModelSimFPGA Prog.GXSLoad4 Select Start=>Programs=>Xilinx Foundation 4=>Accessories=>CORE Generator System  Select “Create a new project”  Create a new project in “I:\xilinx\tutorial\cores” as shown in the figure below and click OK.  Make sure that you read the message and Click OK  Double click on “Math Functions”=> “Adders & Subtracters”=> “Adder Subtracter” as shown.5 Double Click “Adder Subtractor.” You will see the following display. Note that the core type is called “logicore” version 5.0 and the vendor is Xilinx, Inc. • Cores from other vendors are usually unavailable unless we pay for them. • Customize and generate the core  Input the parameters exactly as shown above then click the “Generate” button.  Use the Windows Explorer to view the “I:\xilinx\tutorial\cores” directory. You should see the following files: adder.edn, adder.veo, adder.v, adder.xco and adder.xcp as generated by Core Generator System.  Click on the “Data Sheet” button to view information about this core.6 • Open “adder.veo” using the HDL Editor.  This file contains the instantiation template for the adder module.  Note that “adder” instantiation has already been put in “mac.v”. • The “adder.v” is the behavioral model for the adder core to be used in