Xilinx HDL Coding HintsComparing Synthesis and Simulation ResultsOmit the Wait for XX ns StatementOmit the ...After XX ns or Delay StatementUse Case and If-Else StatementsOrder and Group Arithmetic FunctionsOmit Initial ValuesSelecting HDL Formatting StylesSelecting a Capitalization StyleUsing Xilinx Naming ConventionsMatching File Names to Entity and Module NamesNaming Identifiers, Types, and PackagesUsing LabelsUsing Variables for Constants (VHDL Only)Using Parameters for Constants (Verilog Only)Using Named and Positional AssociationManaging Your DesignCreating Readable CodeUsing Std_logic Data Type (VHDL only)Comparing Signals and Variables (VHDL only)Figure 1-1 Gate implementation of XOR_SIGFigure 1-2 Gate Implementation of XOR_VARUsing Schematic Design Hints with HDL DesignsBarrel Shifter DesignImplementing Latches and RegistersFigure 1-3 D Latch Implemented with GatesFigure 1-4 D Latch Implemented by Instantiating a RAMTable 1-5 D Latch Implementation ComparisonResource SharingFigure 1-5 Implementation of Resource SharingFigure 1-6 Implementation without Resource SharingTable 1-6 Resource Sharing/No Resource Sharing Comparison for XC4005EPC84-2Gate ReductionPreset Pin or Clear PinFigure 1-7 XC4000 Configurable Logic BlockFigure 1-8 Implementation of Gated ClockFigure 1-9 Implementation of Clock EnableUsing If StatementsUsing Case StatementsUsing Nested If StatementsFigure 1-10 Implementation of Nested IfFigure 1-11 Implementation of If-CaseComparing If Statement and Case StatementFigure 1-12 If_Ex ImplementationFigure 1-13 Case_Ex ImplementationSynthesis and Simulation Design Guide — 0401738 01 -1Xilinx HDL Coding HintsHDLs contain many complex constructs that are difficult to under-stand at first. Also, the methods and examples included in HDL manuals do not always apply to the design of FPGAs. If you currently use HDLs to design ASICs, your established coding style may unnecessarily increase the number of gates or CLB levels in FPGA designs. HDL synthesis tools implement logic based on the coding style of your design. To learn how to efficiently code with HDLs, you can attend training classes, read reference and methodology notes, and refer to synthesis guidelines and templates available from Xilinx and the synthesis vendors. When coding your designs, remember that HDLs are mainly hardware description languages. You should try to find a balance between the quality of the end hardware results and the speed of simulation.The coding hints and examples included in this chapter are not intended to teach you every aspect of VHDL or Verilog, but they should help you develop an efficient coding style.The following sections are included in this chapter.• “Comparing Synthesis and Simulation Results”• “Selecting HDL Formatting Styles”• “Using Schematic Design Hints with HDL Designs”Comparing Synthesis and Simulation ResultsVHDL and Verilog are hardware description and simulation languages that were not originally intended as input to synthesis. Therefore, many hardware description and simulation constructs are not supported by synthesis tools. In addition, the various synthesis tools use different subsets of VHDL and Verilog. VHDL and Verilog semantics are well defined for design simulation. The synthesis tools must adhere to these semantics to ensure that designs simulate the same way before and after synthesis. Follow the guidelines presented below to create code that simulates the same way before and after synthesis.Synthesis and Simulation Design Guide-2 Xilinx Development SystemOmit the Wait for XX ns StatementDo not use the Wait for XX ns statement in your code. XX specifies the number of nanoseconds that must pass before a condition is executed. This statement does not synthesize to a component. In designs that include this statement, the functionality of the simulated design does not match the functionality of the synthesized design. VHDL and Verilog examples of the Wait for XX ns statement are as follows.•VHDLwait for XX ns;•Verilog#XX;Omit the ...After XX ns or Delay StatementDo not use the ...After XX ns statement in your VHDL code or the Delay assignment in your Verilog code. Examples of these statements are as follows.•VHDL(Q <=0 after XX ns)•Verilogassign #XX Q=0;XX specifies the number of nanoseconds that must pass before a condition is executed. This statement is usually ignored by the synthesis tool. In this case, the functionality of the simulated design does not match the functionality of the synthesized design.Xilinx HDL Coding HintsSynthesis and Simulation Design Guide -3Use Case and If-Else StatementsYou can use If-Else statements, Case statements, or other conditional code to create state machines or other conditional logic. These state-ments implement the functions differently, however, the simulated designs are identical. The If-Else statement generally specifies priority-encoded logic and the Case statement generally specifies balanced behavior. The If-Else statement can, in some cases, result in a slower circuit overall. These statements vary with the synthesis tool. Refer to the “Comparing If Statement and Case Statement” section of this chapter for more information. Order and Group Arithmetic FunctionsThe ordering and grouping of arithmetic functions can influence design performance. For example, the following two VHDL state-ments are not necessarily equivalent.ADD <= A1 + A2 + A3 + A4;ADD <= (A1 + A2) + (A3 + A4);For Verilog, the following two statements are not necessarily equiva-lent.ADD = A1 + A2 + A3 + A4;ADD = (A1 + A2) + (A3 + A4);The first statement cascades three adders in series. The second state-ment creates two adders in parallel: A1 + A2 and A3 + A4. In the second statement, the two additions are evaluated in parallel and the results are combined with a third adder. RTL simulation results are the same for both statements, however, the second statement results in a faster circuit after synthesis (depending on the bit width of the input signals).Although the second statement generally results in a faster circuit, in some cases, you may want to use the first statement. For example, if the A4 signal reaches the adder later than the other signals, the first statement produces a faster implementation because the cascaded structure creates fewer logic levels for A4. This structure allows A4 to catch up to the other signals. In this case, A1 is the fastest signal followed by A2 and A3; A4 is the