UW-Madison ECE 554 - Xilinx HDL Coding Hints (60 pages)

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Xilinx HDL Coding Hints



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Xilinx HDL Coding Hints

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Pages:
60
School:
University of Wisconsin, Madison
Course:
Ece 554 - Digital Engineering Laboratory
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Xilinx HDL Coding Hints HDLs contain many complex constructs that are difficult to understand at first Also the methods and examples included in HDL manuals do not always apply to the design of FPGAs If you currently use HDLs to design ASICs your established coding style may unnecessarily increase the number of gates or CLB levels in FPGA designs HDL synthesis tools implement logic based on the coding style of your design To learn how to efficiently code with HDLs you can attend training classes read reference and methodology notes and refer to synthesis guidelines and templates available from Xilinx and the synthesis vendors When coding your designs remember that HDLs are mainly hardware description languages You should try to find a balance between the quality of the end hardware results and the speed of simulation The coding hints and examples included in this chapter are not intended to teach you every aspect of VHDL or Verilog but they should help you develop an efficient coding style The following sections are included in this chapter Comparing Synthesis and Simulation Results Selecting HDL Formatting Styles Using Schematic Design Hints with HDL Designs Comparing Synthesis and Simulation Results VHDL and Verilog are hardware description and simulation languages that were not originally intended as input to synthesis Therefore many hardware description and simulation constructs are not supported by synthesis tools In addition the various synthesis tools use different subsets of VHDL and Verilog VHDL and Verilog semantics are well defined for design simulation The synthesis tools must adhere to these semantics to ensure that designs simulate the same way before and after synthesis Follow the guidelines presented below to create code that simulates the same way before and after synthesis Synthesis and Simulation Design Guide 0401738 01 1 Synthesis and Simulation Design Guide Omit the Wait for XX ns Statement Do not use the Wait for XX ns statement in your code XX specifies the number of nanoseconds that must pass before a condition is executed This statement does not synthesize to a component In designs that include this statement the functionality of the simulated design does not match the functionality of the synthesized design VHDL and Verilog examples of the Wait for XX ns statement are as follows VHDL wait for XX ns Verilog XX Omit the After XX ns or Delay Statement Do not use the After XX ns statement in your VHDL code or the Delay assignment in your Verilog code Examples of these statements are as follows VHDL Q 0 after XX ns Verilog assign XX Q 0 XX specifies the number of nanoseconds that must pass before a condition is executed This statement is usually ignored by the synthesis tool In this case the functionality of the simulated design does not match the functionality of the synthesized design 2 Xilinx Development System Xilinx HDL Coding Hints Use Case and If Else Statements You can use If Else statements Case statements or other conditional code to create state machines or other conditional logic These statements implement the functions differently however the simulated designs are identical The If Else statement generally specifies priority encoded logic and the Case statement generally specifies balanced behavior The If Else statement can in some cases result in a slower circuit overall These statements vary with the synthesis tool Refer to the Comparing If Statement and Case Statement section of this chapter for more information Order and Group Arithmetic Functions The ordering and grouping of arithmetic functions can influence design performance For example the following two VHDL statements are not necessarily equivalent ADD A1 A2 A3 A4 ADD A1 A2 A3 A4 For Verilog the following two statements are not necessarily equivalent ADD A1 A2 A3 A4 ADD A1 A2 A3 A4 The first statement cascades three adders in series The second statement creates two adders in parallel A1 A2 and A3 A4 In the second statement the two additions are evaluated in parallel and the results are combined with a third adder RTL simulation results are the same for both statements however the second statement results in a faster circuit after synthesis depending on the bit width of the input signals Although the second statement generally results in a faster circuit in some cases you may want to use the first statement For example if the A4 signal reaches the adder later than the other signals the first statement produces a faster implementation because the cascaded structure creates fewer logic levels for A4 This structure allows A4 to catch up to the other signals In this case A1 is the fastest signal followed by A2 and A3 A4 is the slowest signal Synthesis and Simulation Design Guide 3 Synthesis and Simulation Design Guide Most synthesis tools can balance or restructure the arithmetic operator tree if timing constraints require it However Xilinx recommends that you code your design for your selected structure Omit Initial Values Do not assign signals and variables initial values because initial values are ignored by most synthesis tools The functionality of the simulated design may not match the functionality of the synthesized design For example do not use initialization statements like the following VHDL and Verilog statements VHDL variable SUM INTEGER 0 Verilog wire SUM 1 b0 Selecting HDL Formatting Styles Because HDL designs are often created by design teams Xilinx recommends that you agree on a style for your code at the beginning of your project An established coding style allows you to read and understand code written by your fellow team members Also inefficient coding styles can adversely impact synthesis and simulation which can result in slow circuits Additionally because portions of existing HDL designs are often used in new designs you should follow coding standards that are understood by the majority of HDL designers This section of the manual provides a list of suggested coding styles that you should establish before you begin your designs Selecting a Capitalization Style Select a capitalization style for your code Xilinx recommends using a consistent style lower or upper case for entity or module names in FPGA designs 4 Xilinx Development System Xilinx HDL Coding Hints Verilog For Verilog the following style is recommended Use lower case letters for the following Module names Verilog language keywords Use upper case letters for the following Labels Reg wire instance and


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