The Xilinx Virtex Series FPGA 11/19/2003 ECE 554 1The Xilinx Virtex Series FPGA• Virtex FPGA Structure• Specific Features–IOB– CLB - Function Generators, Flip-Flops, SRAM, and Fast Carry Logic– Three-State Buffers– Block SelectRAM– Programmable Routing Matrix– Clock Distribution (Delay-Locked Loops)– Boundary Scan– Configuration• Virtex XCV800-PQ/HQ240 C Characteristics1/19/2003 ECE 554 2• Primary Reference:– On-Line Xilinx Data Sheet DS003 (v.2.5, April 2, 2001) - http://www.xilinx.com/partinfo/ds003.pdf• See Figure 1: Virtex Architecture Overview– IOBs - Input/Output Blocks– CLBs - Configurable Logic Blocks– GRM - General Routing Matrix– 3-state buffers– BRAMs - Block SelectRAM– DLLs - Delay-Locked Loops– VersaRing - I/O interface routing resourcesVirtex FPGA ArchitectureThe Xilinx Virtex Series FPGA 21/19/2003 ECE 554 3Figure 1- Virtex Architecture Overview1/19/2003 ECE 554 4• Logic configured by values stored in SRAM cells– CLBs implement logic in SRAM-stored truth tables– CLBs use SRAM-controlled multiplexers– Routing uses “pass” transistors for making/breaking connections between wire segments• See Table 1: Virtex FPGA Family MembersVirtex FPGA ArchitectureThe Xilinx Virtex Series FPGA 31/19/2003 ECE 554 5Table 1 – Virtex FPGA Family Members1/19/2003 ECE 554 6• See Figure 2: Virtex Input/Output Block• Output Features– Optional data output D flip-flop with clock enable and shared asynchronous Set/Reset– Optional 3-state control D flip-flop with clock enable and shared asynchronous Set/Reset– Three-state output buffer– Independent polarity controls on output buffer and control signalsIOB - Input/Output BlockThe Xilinx Virtex Series FPGA 41/19/2003 ECE 554 7Figure 2: Virtex Input/Output Block1/19/2003 ECE 554 8• Output Features (continued)– Electrostatic discharge (ESD) (protection)– Optional pull-up and pull-down resistors (note comments in documentation on state of pull-ups and pull-down during configuration)– Weak keeper circuit– Wide range of low-voltage signaling standards (See Table 3).– Strong current drive (24 ma source, 48 ma sink)– Drive strength and slew rate controlsIOB - Input/Output BlockThe Xilinx Virtex Series FPGA 51/19/2003 ECE 554 9• Input Features– Input Buffer– Wide range of low-voltage signaling standards– Programmable delay for forcing pad-to-pad hold time to zero– Optional data D flip-flop with clock enable and shared Set/Reset– Optional pull-up and pull-down resistors (Same ones as for output use)IOB - Input/Output Block1/19/2003 ECE 554 10CLB - Configurable Logic Block• See Figure 4: 2-Slice Virtex CLB• Contains two logic cells• Each logic cell contains:– 2 Look-up tables (LUTs)– 2 D flip-flops/latches– Fast carry logic– Three-state drivers– SRAM control logicThe Xilinx Virtex Series FPGA 61/19/2003 ECE 554 11Figure 4: 2-Slice Virtex CLB1/19/2003 ECE 554 12CLB - Configurable Logic Block• See Figure 5: Detailed View of Virtex Slice• Logic Function Implementation– 2 Function Generators - Each a 4-input LUT -implements any 4-input function– F5 multiplexer - combines two LUTs with select input -implements any 5-input function, 4-to-1 mux, or selected functions of up to 9 inputs.– F6 multiplexer - combines outputs of two F5 multiplexer - implements any 6-input function, 8-to-1 mux, or selected functions of up to 19 inputs.– Four direct feedthrough paths - useful to facilitate routing by use of through-the-cell pathsThe Xilinx Virtex Series FPGA 71/19/2003 ECE 554 13Figure 5: Detailed View of Virtex Slice1/19/2003 ECE 554 14CLB - Configurable Logic Block• Storage Elements– 2 D flip-flops/latches– Optionally included in cell output paths– Shared clock enable– Shared synchronous/asynchronous Set/Reset signals• SR - forces storage element into initialization state specified• BY - forces storage element into opposite state– All control signals independently invertibleThe Xilinx Virtex Series FPGA 81/19/2003 ECE 554 15CLB - Configurable Logic Block• Fast Carry Logic (See Figure 5)– Two chains of two bits per CLB– AND gate, 0/1 Mux, CY Mux, EXOR– Manchester Carry Chain-Like• 3-state Drivers (BUFT) - on-chip drivers with independent control (T and E) and input pins• Distributed LUT SelectRAMs - Per logic cell, one of:• Two 16 x 1-bit synchronous RAM• 16 x 2-bit synchronous RAM• 32 x 1-bit synchronous RAM• 16 x 1 dual-port synchronous RAM• Two 16-bit shift registers 1/19/2003 ECE 554 16Block SelectRAM• Fully synchronous dual-ported 4096-bit RAM– Stores address, data and write-control signal on inputs– Cannot change address, even for read without using clock– For dual port use, interesting timing restrictions– See App Note XAPP130 http://www.xilinx.com/xapp/xapp130.pdf• Organized in vertical columns of blocks on left and right of CLB array• Block height is 4 CLBs => Number of block per column is (height of CLB of array)/4• See Table 3: Virtex Block SelectRAM Amounts• See Figure 6: Dual-Port Block SelectRAM• Independent control signals for each port• See Table 4: Block SelectRAM Port Aspect Ratios• Ratios independently selectableThe Xilinx Virtex Series FPGA 91/19/2003 ECE 554 17Tables 3 & 4 and Figure 61/19/2003 ECE 554 18Programmable Routing Matrix• Local Routing– See Figure 7: Virtex Local Routing– Interconnections among LUTs, flip-flops, and General Routing Matrix (GRM)– Internal CLB feedback paths that can chain LUTs together– Direct paths between horizontally-adjacent CLBs– Short connections with few “pass” transistors => low delay => high-speed connectionsThe Xilinx Virtex Series FPGA 101/19/2003 ECE 554 19Figure 7: Virtex Local Routing1/19/2003 ECE 554 20Programmable Routing Matrix• General Purpose Routing– Majority of interconnect resources– In horizontal and vertical routing channels associated with rows and columns of CLBs– GRM - Switch matrix through which horizontal and vertical routing resources connect and means by which CLBs access general purpose routing• 24 single-length lines between adjacent GRMs in 4 directions• 72 buffered hex lines route GRM signals to other GRMs 6 blocks away in 4 directions• 12 longlines are buffered bidirectional wires that distribute signals across the device– Vertical - span full device height– Horizontal - span full device widthThe Xilinx Virtex Series FPGA 111/19/2003 ECE 554 21Programmable Routing
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