FeaturesDescriptionVirtex ArchitectureHigher PerformanceArchitectural DescriptionVirtex ArrayInput/Output BlockInput PathOutput PathI/O BankingConfigurable Logic BlockLook-Up TablesStorage ElementsAdditional LogicArithmetic LogicBUFTsBlock SelectRAMProgrammable Routing MatrixLocal RoutingGeneral Purpose RoutingI/O RoutingDedicated RoutingGlobal RoutingClock DistributionDelay-Locked Loop (DLL)Boundary ScanInstruction SetData RegistersBit SequenceIdentification RegistersIncluding Boundary Scan in a DesignDevelopment SystemDesign ImplementationDesign VerificationConfigurationConfiguration ModesSlave Serial ModeMaster Serial ModeSelectMAP ModeWriteAbortBoundary-Scan ModeConfiguration SequenceDelaying ConfigurationStart-Up SequenceData Stream FormatReadbackVirtex Electrical CharacteristicsDefinition of TermsAll specifications are subject to change without notice.Virtex DC CharacteristicsAbsolute Maximum RatingsRecommended Operating ConditionsDC Characteristics Over Recommended Operating ConditionsPower-On Power Supply RequirementsDC Input and Output levelsVirtex Switching CharacteristicsIOB Input Switching CharacteristicsIOB Input Switching Characteristics Standard AdjustmentsIOB Output Switching CharacteristicsIOB Output Switching Characteristics Standard AdjustmentsCalculation of Tioop as a Function of CapacitanceClock Distribution GuidelinesClock Distribution Switching CharacteristicsI/O Standard Global Clock Input AdjustmentsCLB Switching CharacteristicsCLB Arithmetic Switching CharacteristicsCLB SelectRAM Switching CharacteristicsBlock RAM Switching CharacteristicsTBUF Switching CharacteristicsJTAG Test Access Port Switching CharacteristicsVirtex Pin-to-Pin Output Parameter GuidelinesGlobal Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLLGlobal Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLLMinimum Clock to Out for Virtex DevicesVirtex Pin-to-Pin Input Parameter GuidelinesGlobal Clock Set-Up and Hold for LVTTL Standard, with DLLGlobal Clock Set-Up and Hold for LVTTL Standard, without DLLDLL Timing ParametersDLL Clock Tolerance, Jitter, and Phase InformationVirtex Pin DefinitionsVirtex Pin OutsPin-Out TablesPin-Out DiagramsCS144 Pin Function DiagramTQ144 Pin Function DiagramPQ240/HQ240 Pin Function DiagramBG256 Pin Function DiagramBG352 Pin Function DiagramBG432 Pin Function DiagramBG560 Pin Function DiagramFG256 Pin Function DiagramFG456 Pin Function DiagramFG676 Pin Function DiagramFG680 Pin Function DiagramVirtex Device/Package Combinations and Maximum I/OVirtex Ordering InformationRevision HistoryDS003 (v.2.2) May 23, 2000 - Final Product Specification 16023Features• Fast, high-density Field-Programmable Gate Arrays- Densities from 50k to 1M system gates- System performance up to 200 MHz- 66-MHz PCI Compliant- Hot-swappable for Compact PCI• Multi-standard SelectIO™ interfaces- 16 high-performance interface standards- Connects directly to ZBTRAM devices• Built-in clock-management circuitry- Four dedicated delay-locked loops (DLLs) for advanced clock control- Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets • Hierarchical memory system- LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register- Configurable synchronous dual-ported 4k-bit RAMs- Fast interfaces to external high-performance RAMs• Flexible architecture that balances speed and density- Dedicated carry logic for high-speed arithmetic- Dedicated multiplier support- Cascade chain for wide-input functions- Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset- Internal 3-state bussing- IEEE 1149.1 boundary-scan logic- Die-temperature sensor diode• Supported by FPGA Foundation™ and Alliance Development Systems- Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager- Wide selection of PC and workstation platforms• SRAM-based in-system configuration- Unlimited re-programmability- Four programming modes•0.22 µm 5-layer metal process• 100% factory testedDescriptionThe Virtex FPGA family delivers high-performance,high-capacity programmable logic solutions. Dramaticincreases in silicon efficiency result from optimizing thenew architecture for place-and-route efficiency and exploit-ing an aggressive 5-layer-metal 0.22-µm CMOS process.These advances make Virtex FPGAs powerful and flexiblealternatives to mask-programmed gate arrays. The Virtexfamily comprises the nine members shown in Table 1.Building on experience gained from previous generationsof FPGAs, the Virtex family represents a revolutionary stepforward in programmable logic design. Combining a widevariety of programmable system features, a rich hierarchyof fast, flexible interconnect resources, and advanced pro-cess technology, the Virtex family delivers a high-speedand high-capacity programmable logic solution thatenhances design flexibility while reducing time-to-market.0Virtex™ 2.5 VField Programmable Gate ArraysDS003 (v.2.2) May 23, 2000 03*Final Product SpecificationRTable 1: Virtex Field-Programmable Gate Array Family Members.Device System Gates CLB Array Logic CellsMaximum Available I/OBlock RAM BitsMaximum SelectRAM+™ BitsXCV50 57,906 16x24 1,728 180 32,768 24,576XCV100 108,904 20x30 2,700 180 40,960 38,400XCV150 164,674 24x36 3,888 260 49,152 55,296XCV200 236,666 28x42 5,292 284 57,344 75,264XCV300 322,970 32x48 6,912 316 65,536 98,304XCV400 468,252 40x60 10,800 404 81,920 153,600XCV600 661,111 48x72 15,552 512 98,304 221,184XCV800 888,439 56x84 21,168 512 114,688 301,056XCV1000 1,124,022 64x96 27,648 512 131,072 393,216Virtex™ 2.5 V Field Programmable Gate Arrays2 DS003 (v.2.2) May 23, 2000 - Final Product Specification RVirtex ArchitectureVirtex devices feature a flexible, regular architecture thatcomprises an array of configurable logic blocks (CLBs) sur-rounded by programmable input/output blocks (IOBs), allinterconnected by a rich hierarchy of fast, versatile routingresources. The abundance of routing resources permits theVirtex family to accommodate even the largest and mostcomplex designs.Virtex FPGAs are SRAM-based, and are customized byloading configuration data into internal memory cells. Insome modes, the FPGA reads its own configuration datafrom an external PROM (master serial mode). Otherwise,the configuration data is written into the FPGA (Select-MAP™, slave serial, and JTAG modes).The standard Xilinx Foundation™ and