1/26/2002 1Verilog HDL IntroductionECE 554 Digital Engineering LaboratoryCharles R. Kime1/28/2001 2Overview Simulation and Synthesis Modules and Primitives Styles Structural Descriptions Language Conventions Data Types Delay Behavioral Constructs Compiler Directives Simulation and Testbenches1/28/2001 3Simulation and Synthesis Simulation tools typically accept full set of Verilog language constructs Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools Synthesis tools typically accept only a subset of the full Verilog language constructs• In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics• There are other restrictions not detailed here, see [2].1/28/2001 4Modules  The Module Concept• Basic design unit• Modules are:DeclaredInstantiated• Modules declarations cannot be nested1/28/2001 5Module Declaration (FIO*) Syntaxmodule_declaration::= module_keyword module_identifier [list of ports];{module_item} endmodulemodule_keyword ::= module|macromodulelist_of_ports::= (port {, port})* For Information Only – not to be covered in presentation1/28/2001 6Module Declaration (FIO) Syntax (continued)module_item::= module_item_declaration | parameter_override | continuous_assign | gate_instantiation | udp_instantiation | module_instantiation | specify_block | initial_construct | always_constructmodule_item_declaration::= parameter_declaration | input_declaration | output_declaration | inout_declaration | net_declaration | reg_declaration | integer_declaration | real_declaration | time_declaration | realtime_declaration | event_declaration | task_declaration | function_declarationparameter_override ::= defparamlist_of_parameter_assignmentsudp declaration1/28/2001 7Module Declaration Annotated Example/* module_keyword module_identifier (list of ports) */module C_2_4_decoder_with_enable (A, E_n, D) ; input [1:0] A ; // input_declarationinput E_n ; // input_declarationoutput [3:0] D ; // output_declarationassign D = {4{~E_n}} & ((A == 2'b00) ? 4'b0001 :(A == 2'b01) ? 4'b0010 :(A == 2'b10) ? 4'b0100 :(A == 2'b11) ? 4'b1000 :4'bxxxx) ; // continuous_assignendmodule1/28/2001 8Module Declaration Identifiers - must not be keywords! Ports• First example of signals • Scalar: e. g., E_n• Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3] Range is MSB to LSB Can refer to partial ranges - D[2:1]• Type: defined by keywordsinputoutputinout (bi-directional)1/28/2001 9Module Instantiationmodule C_4_16_decoder_with_enable (A, E_n, D) ; input [3:0] A ; input E_n ; output [15:0] D ; wire [3:0] S;wire[3:0] S_n;C_2_4_decoder_with_enable DE (A[3:2], E_n, S);not N0 (S_n, S);C_2_4_decoder_with_enable D0 (A[1:0], S_n[0], D[3:0]);C_2_4_decoder_with_enable D1 (A[1:0], S_n[1], D[7:4]);C_2_4_decoder_with_enable D2 (A[1:0], S_n[2], D[11:8]);C_2_4_decoder_with_enable D3 (A[1:0], S_n[3], D[15:12]);endmodule  Example1/28/2001 10Module Instantiation (FIO)module _instantiation ::= module_identifier [parameter_value_assign ment] module_instance {, module_instance}; parameter_value_assignment ::= # (expression {, expression})module_instance ::= name_of_in stance ([list_of_module_connections])name_of_instance ::= module_instance_identifier [range]list of module connections ::=ordered_port_connection {, ordered_port_connection}| named_port_conn ection {, named _port_con nec tion}ordered_port_connection ::= [expression]named_port_connection ::= . port_identifier ([expression]) Syntax1/28/2001 11Module Instantiation• Single module instantiation for five module instancesC_2_4_decoder_with_enable DE (A[3:2], E_n, S),D0 (A[1:0], S_n[0], D[3:0]),D1 (A[1:0], S_n[1], D[7:4]),D2 (A[1:0], S_n[2], D[11:8]),D3 (A[1:0], S_n[3], D[15:12]);• Named_port connectionC_2_4_decoder_with_enable DE (.E_n (E_n), .A (A[3:2]) .D (S));// Note order in list no longer important (E_n and A interchanged). More Examples1/28/2001 12Primitives Gate Level• and, nand• or, nor• xor, xnor• buf , not• bufif0, bufif1, notif0, notif1 (three-state) Switch Level• *mos where * is n, p, c, rn, rp, rc; pullup, pulldown;*tran+where * is (null), r and +(null), if0, if1 with both * and +not (null)1/28/2001 13Primitives No declaration; can only be instantiated All output ports appear in list before any input ports  Optional drive strength, delay, name of instance Example: and N25 (Z, A, B, C); //instance name Example: and #10 (Z, A, B, X); // delay(X, C, D, E); //delay/*Usually better to provide instance name for debugging.*/ Example: or N30 (SET, Q1, AB, N5),  N41 (N25, ABC, R1);1/28/2001 14Styles Structural - instantiation of primitives and modules RTL/Dataflow - continuous assignments Behavioral - procedural assignments 1/28/2001 15Style Example - Structuralmodulehalf_add (X, Y, S, C);inputX, Y ;outputS, C ;xor(S, X, Y) ;and(C, X, Y) ;endmodulemodulefull_add (A, B, CI, S, CO) ;inputA, B, CI ;output S, CO ;wireN1, N2, N3;half_add HA1 (A, B, N1, N2),HA2 (N1, CI, S, N3);orP1 (CO, N3, N2);endmodule 1/28/2001 16Style Example - RTL/Dataflowmodule fa_rtl (A, B, CI, S, CO) ;input A, B, CI ;output S, CO ;assign S = A ^ B ^ CI; //continuous assignmentassign CO = A & B | A & CI | B & CI; //continuous assignmentendmodule1/28/2001 17Style Example - Behavioralmodule fa_bhv (A, B, CI, S, CO) ;input A, B, CI ;output S, CO ;reg S, CO; // required to “hold” values between events.always@(A or B or CI) //; beginS <= A ^ B ^ CI; // procedural assignmentCO <= A & B | A & CI | B & CI;// procedural assignment end endmodule 1/28/2001 18Structural Descriptions Textual description of schematic Form of netlist Connections Hierarchy Arrays of instances Hierarchy established by instantiation of modules and primitives within modules1/28/2001 19Connections By position association• module C_2_4_decoder_with_enable (A, E_n, D);• C_4_16_decoder_with_enable DX (X[3:2], W_n, word);• A = X[3:2], E_n = W_n, D = word By name association• module C_2_4_decoder_with_enable (A, E_n, D);• C_2_4_decoder_with_enable DX (.E_n(W_n), .A(X[3:2]), .D(word));• A = X[3:2], E_n = W_n, D = word1/28/2001 20Connections Empty Port Connections• module C_2_4_decoder_with_enable (A, E_n, D);• C_2_4_decoder_with_enable DX (X[3:2], , word);• E_n is at high-impedance state