Verilog HDL IntroductionOverviewSimulation and SynthesisModulesModule DeclarationSlide 6Module InstantiationSlide 8PrimitivesSlide 10StylesStyle Example - StructuralStyle Example - RTL/DataflowStyle Example - BehavioralConnectionsSlide 17Arrays of InstancesLanguage ConventionsSlide 20Logic ValuesNumber RepresentationSlide 23VariablesData Types - Nets - SemanticsNet ExamplesInitial Value & Undeclared NetsData Types - Register SemanticsRegister AssignmentRegister ExamplesStringsConstants (Paramters)OperatorsExpression Bit WidthsSlide 35Expression Bit Widths (continued)Slide 37Slide 38Expressions with Operands Containing x or zSlide 40Simulation Time ScalesSimulation Time Scales (continued)Behavioral ConstructsBehavioral Constructs (continued)Slide 45Behavioral Constructs - ExampleProcedural AssignmentsProcedural Assignments - Some RulesProcedural Timing, Controls & SynchronizationSlide 50Slide 51Slide 52Slide 53Procedural Timing, Controls & Synchronization (FIO)Blocking AssignmentsNon-Blocking AssignmentsBlocking Assignments - Inter-Assignment DelaySlide 58Non-Blocking Assignment - Inter-Assignment DelayNon-Blocking Assignment - Intra-Assignment DelayActivity ControlConditional Operatorcase Statementcasex Statementcasez StatementConditional (if … else) Statement ExampleConditional (if … else) Statement (continued)for Loop Examplewhile Loop Exampleforever Loop ExampleTasksTask ExampleFunctionsFunction ExampleCompiler DirectivesCompiler Directives (Continued)Testbench ApproachStimulus Generation ExampleStimulus Generation Example (Continued)References1/24/2006 1Verilog HDL IntroductionECE 554 Digital Engineering LaboratoryCharles R. Kime and Michael J. Schulte(Updated: Kewal K. Saluja)1/24/2006 2OverviewSimulation and SynthesisModules and PrimitivesStylesStructural DescriptionsLanguage ConventionsData TypesDelayBehavioral ConstructsCompiler DirectivesSimulation and Testbenches1/24/2006 3Simulation and SynthesisSimulation tools typically accept full set of Verilog language constructsSome language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis toolsSynthesis tools typically accept only a subset of the full Verilog language constructs•In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics•There are other restrictions not detailed here, see [2].1/24/2006 4Modules The Module Concept•Basic design unit•Modules are:DeclaredInstantiated•Modules declarations cannot be nested1/24/2006 5Module DeclarationAnnotated Example/* module_keyword module_identifier (list of ports) */module C_2_4_decoder_with_enable (A, E_n, D) ; input [1:0] A ; // input_declarationinput E_n ; // input_declarationoutput [3:0] D ; // output_declarationassign D = {4{~E_n}} & ((A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ; // continuous_assignendmodule1/24/2006 6Module DeclarationIdentifiers - must not be keywords!Ports•First example of signals •Scalar: e. g., E_n•Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3]Range is MSB to LSBCan refer to partial ranges - D[2:1]•Type: defined by keywordsinputoutputinout (bi-directional)1/24/2006 7Module Instantiationmodule C_4_16_decoder_with_enable (A, E_n, D) ; input [3:0] A ; input E_n ; output [15:0] D ; wire [3:0] S;wire [3:0] S_n;C_2_4_decoder_with_enable DE (A[3:2], E_n, S);not N0 (S_n, S);C_2_4_decoder_with_enable D0 (A[1:0], S_n[0], D[3:0]);C_2_4_decoder_with_enable D1 (A[1:0], S_n[1], D[7:4]);C_2_4_decoder_with_enable D2 (A[1:0], S_n[2], D[11:8]);C_2_4_decoder_with_enable D3 (A[1:0], S_n[3], D[15:12]);endmodule Example1/24/2006 8Module Instantiation•Single module instantiation for five module instances C_2_4_decoder_with_enable DE (A[3:2], E_n, S),D0 (A[1:0], S_n[0], D[3:0]),D1 (A[1:0], S_n[1], D[7:4]),D2 (A[1:0], S_n[2], D[11:8]),D3 (A[1:0], S_n[3], D[15:12]);•Named_port connection C_2_4_decoder_with_enable DE (.E_n (E_n), .A (A[3:2]) .D (S));// Note order in list no longer important (E_n and A interchanged).More Examples1/24/2006 9PrimitivesGate Level•and, nand•or, nor•xor, xnor•buf , not•bufif0, bufif1, notif0, notif1 (three-state)Switch Level•*mos where * is n, p, c, rn, rp, rc; pullup, pulldown; *tran+ where * is (null), r and + (null), if0, if1 with both * and + not (null)1/24/2006 10PrimitivesNo declaration; can only be instantiatedAll output ports appear in list before any input ports Optional drive strength, delay, name of instanceExample: and N25 (Z, A, B, C); //instance nameExample: and #10 (Z, A, B, X); // delay (X, C, D, E); //delay/*Usually better to provide instance name for debugging.*/Example: or N30 (SET, Q1, AB, N5),  N41 (N25, ABC, R1);Example: and #10 N33(Z, A, B, X); // name + delay1/24/2006 11StylesStructural - instantiation of primitives and modulesRTL/Dataflow - continuous assignmentsBehavioral - procedural assignments1/24/2006 12Style Example - Structuralmodule half_add (X, Y, S, C);input X, Y ;output S, C ;xor (S, X, Y) ;and (C, X, Y) ;endmodulemodule full_add (A, B, CI, S, CO) ;input A, B, CI ;output S, CO ;wire N1, N2, N3;half_add HA1 (A, B, N1, N2), HA2 (N1, CI, S, N3);or P1 (CO, N3, N2); endmodule1/24/2006 13Style Example - RTL/Dataflowmodule fa_rtl (A, B, CI, S, CO) ;input A, B, CI ;output S, CO ;assign S = A ^ B ^ CI; //continuous assignmentassign CO = A & B | A & CI | B & CI; //continuous assignment endmodule1/24/2006 14Style Example - Behavioralmodule fa_bhv (A, B, CI, S, CO) ;input A, B, CI ;output S, CO ;reg S, CO; // required to “hold” values between events.always@(A or B or CI) //; beginS <= A ^ B ^ CI; // procedural assignment CO <= A & B | A & CI | B & CI; // procedural assignment end endmodule1/24/2006 16ConnectionsBy position association•module C_2_4_decoder_with_enable (A, E_n, D);•C_4_16_decoder_with_enable DX (X[3:2], W_n, word);•A = X[3:2], E_n = W_n, D = wordBy name association•module C_2_4_decoder_with_enable (A, E_n, D);•C_2_4_decoder_with_enable DX (.E_n(W_n), .A(X[3:2]), .D(word));•A = X[3:2], E_n = W_n, D = word1/24/2006 17ConnectionsEmpty Port Connections•module C_2_4_decoder_with_enable (A, E_n, D);•C_2_4_decoder_with_enable DX (X[3:2], , word);Input E_n is at high-impedance state