Class ProjectProject AssignmentSample ECE554 Computers – Part 1Sample ECE554 Computers – Part 2Sample ECE554 Computers – Part 3Incorporating Various I/O InterfacesNew FPGA BoardsProject Milestones – Part 1Project Milestones – Part 2Project Milestones – Part 3Project Milestones – Part 4Project Milestones – Part 5Sample Gantt ChartProject Milestones – Part 6Project Milestones – Part 7Project Milestones – Part 8Project Milestones – Part 9Teams in ECE554BrainstormingMultivotingEvaluation in 554Class ProjectSpring 2008ECE554Digital Engineering LaboratoryProject Assignment•Design a non-trivial computer with an original instruction set architecture (ISA)•Four key requirements–It must be an original ISA•Somewhat negotiable–It must be non-trivial–It must be tractable•everything takes at least twice as long as you expect –It must interface through the serial port with the terminal emulator on the lab workstations•Negotiable (always useful for development/debug)•Be creative and have fun! •Leave helpful hints for the future – use “wiki” and update itSample ECE554 Computers – Part 1•A (pipelined) general-purpose 32-bit computer with –A conventional ISA•ADD, SUB, MUL, MOV, LD, ST, JMP, etc. •A gimmick that makes the machine non-trivial–Examples of gimmicks include•Superscalar, VLIW•Multithreading•Pipeline with dynamic branch prediction and data forwarding•Out of order execution•Floating point support•Single instruction, multiple data execution•Specialized instructions•Coprocessor supportSample ECE554 Computers – Part 2•A programmable special-purpose processor–Multimedia Processor–3D Graphics Processor–Binary Coded Decimal (BCD) Processor–String Processor–Security Processor–Fault tolerance support•Examples of very good projects from previous semesters are in lab•Feel free to look at real ISAs, but don’t copy•Make sure your processor can be implemented on the board, but don’t let quirks of the system limit your creativitySample ECE554 Computers – Part 3•Projects should also have significant software components. For example, –Software simulator for your processor –Assembler for your processor–Simple compiler for your processor–Demonstration and testing software•Also good to include hierarchical memory (e.g., cache on FPGA + memory on chip).•Most useful processors will support interrupts•Talk to me and TA about ideas you haveIncorporating Various I/O Interfaces•The Vertex-2 Pro FPGA board has several interfaces that may be useful in implementing or demonstrating your project–Video Graphics Array (VGA) for displaying graphics on the monitor–USB interface – Avoid since it doesn’t work well. –PS/2 interface for mouse/keyboard–Ethernet interface to network–Audio codecs for playing musicBecome familiar with the board and its features early to know strengths/limitations.New FPGA Boards•The new XUP Virtex-II Pro FPGA boards have the following features: –Virtex-II Pro FPGA with PowerPC™ 405 cores–Up to 2 GB of Double Data Rate (DDR) SDRAM–On-board 10/100 Ethernet PHY device–RS-232 DB9 serial port and two PS-2 serial ports–AC-97 audio CODEC with audio amplifier and speaker–XSGA video output–Support for various accessory boards http://www.xilinx.com/univ/accessory_boards.htm•For additional information see:–http://www.xilinx.com/univ/xupv2p.htmlProject Milestones – Part 1•The major steps for the project include: –Form teams (finish doing this today)–Choose one team leader (required)–Define the architecture•Will need to meet outside of lab time•Use brainstorming and multivoting•Dates for all the major milestones are listed on the course syllabus•See website for further details and previous projectsProject Milestones – Part 2–Project Proposal (2/13)•20 to 30 minute presentation (8 to 10 slides)•Your project's targeted application •Processor type (superscalar, out-of-order, dsp, etc.) •Peripherals you plan on using (vga, keyboard, ethernet, etc.) •Other features/gimmicks you plan to include (interrupts, performance counters, etc.) •Supporting software you plan to write (assembler, simulator, etc.). •Gantt chart with your tentative project timeline (Microsoft Project is useful for this) •Good opportunity to get preliminary feedback•All team members attendProject Milestones – Part 3–Architecture review (2/20)•40 minute presentation to instructors (1 hour total)•Full ISA Specification - registers, instruction formats, addressing modes, opcodes, interrupts, exceptions, flags •Other details – gimmicks, peripherals and I/O, memory architecture, planned software, planned user interfaces, etc. •Group leader + other members (all attend)•Let us know if your group needs specific accessory boards (memory, USB, video, etc.)Project Milestones – Part 4–ISA Report (3/25)•Description of visible registers and memory•Description of instruction formats•Descriptions of each instruction•Discussion of I/O interface (and interrupts)•Description of any gimmicks•Other things (e.g., code samples, software overview, diagrams that will help clarify the architecture of your processor)–Define the Microarchitecture•Break the machine into subsystems•Carefully define the interface to each subsystem–signal names, directions, functionality, timing•Sketch out details of each subsystemProject Milestones – Part 5–Microarchitecture review (3/24)•Present your microarchitecture to the instructors (40 minutes => 1 hour)•Present overall microarchitecture (team leader) plus each subsystem (team members)•Describe any changes to ISA or gimmick•Project schedule–Major project tasks (with start and end times)–Project subtasks (with start and end times)–Team members assigned to tasks/subtasks–Gantt chart (www.smartdraw.com or Microsoft Project)Sample Gantt ChartProject Milestones – Part 6–Testing and demo plan (4/7)•Present the plan for integration, debug, and developing demonstration to the instructors (20 minutes => 40 minutes)•Present overall integration plan (team leader) plus status of each subsystem (team members)•Describe what kind of demo you will have to show your projects strengths and features–Describe the main features –Status of the implementation and integration (with start and end times)–Potential debug and test bottlenecks –“What if” some thing does not work