Slide 1AnnouncementsGoals for TodayData Hazard RecapMore HazardsMore HazardsControl HazardsDelay SlotControl Hazards: Speculative ExecutionLoopsBranch PredictionBranch PredictionPipelining: What Could Possibly Go Wrong?Goals for TodayVariationsVariationsVariationsVariationsVariationsVariationsVariationsVariationsNext timePipeline Control Hazardsand Instruction VariationsHakim WeatherspoonCS 3410, Spring 2011Computer ScienceCornell UniversitySee P&H Appendix 4.8 & 2.16 and 2.172AnnouncementsPA1 available: mini-MIPS processorPA1 due next Friday Work in pairsUse your resources•FAQ, class notes, book, Sections, office hours, newsgroup, CSUGLabPrelims: •Thursday, March 10th in class•Thursday, April 28th Evening3Goals for TodayRecap: Data HazardsControl Hazards•What is the next instruction to execute if a branch is taken? Not taken?•How to resolve control hazards•OptimizationsInstruction Variations•ARM•x864Data Hazard RecapDelay Slot(s)•Modify ISA to match implementationStall•Pause current and all subsequent instructionsForward/Bypass•Try to steal correct value from elsewhere in pipeline•Otherwise, fall back to stalling or require a delay slot5More Hazardsbeq r1, r2, Ladd r3, r0, r3sub r5, r4, r6L: or r3, r2, r4datameminstmemDBAPC+46More Hazardsbeq r1, r2, Ladd r3, r0, r3sub r5, r4, r6L: or r3, r2, r4datameminstmemDBAPC+47Control HazardsControl Hazards•instructions are fetched in stage 1 (IF)•branch and jump decisions occur in stage 3 (EX) •i.e. next PC is not known until 2 cycles after branch/jumpDelay Slot•ISA says N instructions after branch/jump always executed–MIPS has 1 branch delay slotStall (+ Zap)•prevent PC update•clear IF/ID pipeline register–instruction just fetched might be wrong one, so convert to nop•allow branch to continue into EX stage8Delay Slotbeq r1, r2, Lori r2, r0, 1L: or r3, r1, r4datameminstmemDBAPC+4branchcalcdecidebranch9Control Hazards: Speculative ExecutionControl Hazards•instructions are fetched in stage 1 (IF)•branch and jump decisions occur in stage 3 (EX) •i.e. next PC not known until 2 cycles after branch/jumpStallDelay SlotSpeculative Execution•“Guess” direction of the branch–Allow instructions to move through pipeline–Zap them later if wrong guess•Useful for long pipelines10Loops11Branch Prediction12Branch Prediction13Pipelining: What Could Possibly Go Wrong?Data hazards•register file reads occur in stage 2 (IF) •register file writes occur in stage 5 (WB)•next instructions may read values soon to be writtenControl hazards•branch instruction may change the PC in stage 3 (EX)•next instructions have already started executingStructural hazards•resource contention•so far: impossible because of ISA and pipeline design14Goals for TodayRecap: Data HazardsControl Hazards•What is the next instruction to execute if a branch is taken? Not taken?•How to resolve control hazards•OptimizationsInstruction Variations•ARM•x8615VariationsMore shifts16VariationsCondition flags17VariationsCondition flags18VariationsCondition flags19VariationsConditional instructionstop: CMP r3, r4SUBGT r3, r3, r4SUBLT r4, r4, r3BNE top20VariationsStack operations & multiple destinations21VariationsString instructionsMOV AX, FFhMOV DI, 5000hMOV CX, 2000hREP STOSB22VariationsVector instructionsvaddubs v3, v1, v223Next timeInstruction Variations•ARM/MIPS (RISC)•Versus x86
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