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CORNELL CS 3410 - RISC, CISC, and Assemblers

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Slide 1AnnouncementsGoals for TodayInstruction Set ArchitectureOne Instruction Set ArchitecturePDP-8Stack BasedAccumulator BasedLoad-StoreAxesComplex Instruction Set ComputersReduced Instruction Set ComputerComplexityRISC vs CISCGoals for TodayExamplescs3410 Recap/QuizExample 1ReferencesExample 2Example 2 (better)LessonsPseudo-InstructionsAssemblerMotivationStagesAnatomy of an executing programExample programmath.scalc.sNext timeRISC, CISC, and AssemblersHakim WeatherspoonCS 3410, Spring 2011Computer ScienceCornell UniversitySee P&H Appendix B.1-2, and Chapters 2.8 and 2.122AnnouncementsPA1 due this Friday Work in pairsUse your resources•FAQ, class notes, book, Sections, office hours, newsgroup, CSUGLabPrelims1: next Thursday, March 10th in class•Material covered•Appendix C (logic, gates, FSMs, memory, ALUs) •Chapter 4 (pipelined [and non-pipeline] MIPS processor with hazards)•Chapters 2 and Appendix B (RISC/CISC, MIPS, and calling conventions)•Chapter 1 (Performance)•HW1, HW2, PA1, PA2•Practice prelims are online in CMS•Closed Book: cannot use electronic device or outside material•We will start at 1:25pm sharp, so come early3Goals for TodayInstruction Set Architetures•Arguments: stack-based, accumulator, 2-arg, 3-arg•Operand types: load-store, memory, mixed, stacks, …•Complexity: CISC, RISCAssemblers•assembly instructions•psuedo-instructions•data and layout directives•executable programs4Instruction Set ArchitectureISA defines the permissible instructions•MIPS: load/store, arithmetic, control flow, …•ARM: similar to MIPS, but more shift, memory, & conditional ops•VAX: arithmetic on memory or registers, strings, polynomial evaluation, stacks/queues, …•Cray: vector operations, …•x86: a little of everything5One Instruction Set ArchitectureToy example: subleq a, b, targetMem[b] = Mem[b] – Mem[a]then if (Mem[b] <= 0) goto targetelse continue with next instructionclear a == subleq a, a, pc+4jmp c == subleq Z, Z, cadd a, b == subleq a, Z, pc+4; subleq Z, b, pc+4; subleq Z, Z, pc+46PDP-8Not-a-toy example: PDP-8One register: ACEight basic instructions:AND a # AC = AC & MEM[a]TAD a # AC = AC + MEM[a]ISZ a # if (!++MEM[a]) skip nextDCA a # MEM[a] = AC; AC = 0JMS a # jump to subroutine (e.g. jump and link)JMP a # jump to MEM[a]IOT x # input/output transferOPR x # misc operations on AC7Stack BasedStack machine•data stack in memory, stack pointer register•Operands popped/pushed as neededadd[ Java Bytecode, PostScript, odd CPUs, some x86 ]Tradeoffs:8Accumulator BasedAccumulator machine•Results usually put in dedicated accumulator registeradd bstore b[ Some x86 ]Tradeoffs:9Load-StoreLoad/store (register-register) architecture•computation only between registers[ MIPS, some x86 ]Tradeoffs:10AxesAxes:•Arguments: stack-based, accumulator, 2-arg, 3-arg•Operand types: load-store, memory, mixed, stacks, …•Complexity: CISC, RISC11Complex Instruction Set ComputersPeople programmed in assembly and machine code!•Needed as many addressing modes as possible•Memory was (and still is) slowCPUs had relatively few registers•Register’s were more “expensive” than external mem•Large number of registers requires many bits to indexMemories were small•Encoraged highly encoded microcodes as instructions•Variable length instructions, load/store, conditions, etc12Reduced Instruction Set ComputerDave Patterson•RISC Project, 1982•UC Berkeley•RISC-I: ½ transtisters & 3x faster•Influences: Sun SPARC, namesake of industryJohn L. Hennessy•MIPS, 1981•Stanford•Simple pipelining, keep full•Influences: MIPS computer system, PlayStation, Nintendo13ComplexityMIPS = Reduced Instruction Set Computer (RlSC)•≈ 200 instructions, 32 bits each, 3 formats•all operands in registers–almost all are 32 bits each•≈ 1 addressing mode: Mem[reg + imm]x86 = Complex Instruction Set Computer (ClSC)•> 1000 instructions, 1 to 15 bytes each•operands in dedicated registers, general purpose registers, memory, on stack, …–can be 1, 2, 4, 8 bytes, signed or unsigned•10s of addressing modes–e.g. Mem[segment + reg + reg*scale + offset]14RISC vs CISCRISC PhilosophyRegularity & simplicityLeaner means fasterOptimize the common caseCISC RebuttalCompilers can be smartTransistors are plentifulLegacy is importantCode size countsMicro-code!15Goals for TodayInstruction Set Architetures•Arguments: stack-based, accumulator, 2-arg, 3-arg•Operand types: load-store, memory, mixed, stacks, …•Complexity: CISC, RISCAssemblers•assembly instructions•psuedo-instructions•data and layout directives•executable programs16Examples...T: ADDI r4, r0, -1BEQ r3, r0, BADDI r4, r4, 1LW r3, 0(r3)J TNOPB: ......JAL LnopnopL: LW r5, 0(r31)ADDI r5, r5, 1SW r5, 0(r31)...17cs3410 Recap/Quiz17int x = 10;x = 2 * x + 15;Ccompileraddi r5, r0, 10muli r5, r5, 2addi r5, r5, 15MIPSassembly001000000000010100000000000010100000000000000101001010000100000000100000101001010000000000001111machinecodeassemblerCPUCircuitsGatesTransistorsSilicon18Example 1...T: ADDI r4,r0,-1BEQ r3, r0, BADDI r4,r4, 1LW r3, 0(r3)J TNOPB: ......00100000010000100010001100001000000000000000000000000000000000...19ReferencesQ: How to resolve labels into offsets and addresses?A: Two-pass assembly•1st pass: lay out instructions and data, and builda symbol table (mapping labels to addresses) as you go•2nd pass: encode instructions and data in binary, using symbol table to resolve references20Example 2...JAL LnopnopL: LW r5, 0(r31)ADDI r5,r5,1SW r5, 0(r31)......00100000000100000000000000000100 0000000000000000000000000000000000000000000000000000000000000000100011111110010100000000000000000010000010100101000000000000000100000000000000000000000000000000...21Example 2 (better).text 0x00400000 # code segment...ORI r4, r0, counterLW r5, 0(r4)ADDI r5, r5, 1SW r5, 0(r4)....data 0x10000000 # data segmentcounter: .word 022LessonsLessons:•Mixed data and instructions (von Neumann)•… but best kept in separate segments•Specify layout and data using assembler directives •Use pseudo-instructions23Pseudo-InstructionsPseudo-InstructionsNOP # do nothingMOVE reg, reg # copy between regsLI reg, imm # load immediate (up to 32 bits)LA reg, label # load address (32 bits)B label # unconditional branchBLT reg, reg, label # branch less than24AssemblerAssembler:assembly instructions+ psuedo-instructions+ data and layout directives= executable programSlightly higher level than plain


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