Slide 1Goals for TodayComputer System OrganizationChallengeInterconnectsI/O ControllersI/O ControllersInterconnecting ComponentsBus ParametersBus TypesTypical x86 PC I/O SystemTypical x86 PC I/O SystemI/O Device APISlide 14Communication InterfaceCommunication InterfaceMemory-Mapped I/ODevice DriversCommunication MethodCommunication MethodTypical x86 PC I/O SystemI/O Data TransferDMA: Direct Memory AccessI/O Data TransferDMA: Direct Memory AccessDMA ExampleDMA Issues (1): AddressingDMA ExampleDMA Issues (1): AddressingDMA Issues (2): Virtual MemDMA Issues (4): CachesDMA Issues (4): CachesI/O SummaryI/OHakim WeatherspoonCS 3410, Spring 2011Computer ScienceCornell UniversitySee: P&H Chapter 6.5-62Goals for TodayComputer System OrganizationHow to talk to device? •Programmed I/O or Memory-Mapped I/OHow to get events?•Polling or InterruptsHow to transfer lots of data?•Direct Memory Access (DMA)3Computer System OrganizationComputer System =Input +Output +Memory +Datapath +ControlCPURegistersNetworkVideobusMemorybusDiskUSBAudioKeyboard MouseSerial4ChallengeHow do we interface to other devices•Keyboard•Mouse•Disk•Network•Display•Programmable Timer (for clock ticks)•Audio•Printer(s)•Camera•iPod•Scanner•…5InterconnectsBad Idea #1: Put all devices on one interconnect•We would have to replace all devices as we improve/change the interconnect•keyboard speed == main memory speed ?!CPUNetworkVideoMemoryDiskAudioKeyboardSerialCacheinterconnect6I/O ControllersDecouple via I/O Controllers and “Bridges”•fast/expensive busses when needed; slow/cheap elsewhere•I/O controllers to connect end devices7I/O ControllersDecouple via I/O Controllers and “Bridges”•fast/expensive busses when needed; slow/cheap elsewhere•I/O controllers to connect end devices8Interconnecting ComponentsInterconnects are (were?) busses•parallel set of wires for data and control•shared channel–multiple senders/receivers–everyone can see all bus transactions•bus protocol: rules for using the bus wiresAlternative (and increasingly common):•dedicated point-to-point channels9Bus ParametersWidth = number of wiresTransfer size = data words per bus transactionSynchronous (with a bus clock)or asynchronous (no bus clock / “self clocking”)10Bus TypesProcessor – Memory (“Front Side Bus”. Also QPI)•Short, fast, & wide•Mostly fixed topology, designed as a “chipset”–CPU + Caches + Interconnect + Memory Controller I/O and Peripheral busses (PCI, SCSI, USB, LPC, …)•Longer, slower, & narrower•Flexible topology, multiple/varied connections•Interoperability standards for devices•Connect to processor-memory bus through a bridge11Typical x86 PC I/O System12Typical x86 PC I/O System13I/O Device APITypical I/O Device API•a set of read-only or read/write registersCommand registers•writing causes device to do somethingStatus registers•reading indicates what device is doing, error codes, …Data registers•Write: transfer data to a device•Read: transfer data from a device14Simple (old) example: AT Keyboard Device8-bit Status:8-bit Cmd: 0xAA = “self test”0xAE = “enable kbd”0xED = “set LEDs”…8-bit Data: scancode (when reading) LED state (when writing) or …PE TO AUXB LOCK AL2 SYSF IBS OBS15Communication InterfaceQ: How does program OS code talk to device?A: special instructions to talk over special bussesProgrammed I/O•inb $a, 0x64•outb $a, 0x60•Specifies: device, data, direction•Protection: only allowed in kernel mode*x86: $a implicit; also inw, outw, inh, outh, …16Communication InterfaceQ: How does program OS code talk to device?A: Map registers into virtual address spaceMemory-mapped I/O•Accesses to certain addresses redirected to I/O devices•Data goes over the memory bus•Protection: via bits in pagetable entries•OS+MMU+devices configure mappings17Memory-Mapped I/OKeyboardRegistersVideoRegisters &MemoryAudioRegistersPhysicalAddress SpaceRAMVirtualAddress Space18Device DriversProgrammed I/Ochar read_kbd(){do { sleep(); status = inb(0x64);} while (!(status & 1));return inb(0x60);}Memory Mapped I/Ostruct kbd { char status, pad[3]; char data, pad[3];};kbd *k = mmap(...);char read_kbd(){do { sleep(); status = k->status;} while (!(status & 1));return k->data;}19Communication MethodQ: How does program learn device is ready/done?A: Polling: Periodically check I/O status register•If device ready, do operation•If device done, …•If error, take actionPro? Con?•Predictable timing & inexpensive•But: wastes CPU cycles if nothing to do•Efficient if there is always work to doCommon in small, cheap, or real-time embedded systemsSometimes for very active devices too…20Communication MethodQ: How does program learn device is ready/done?A: Interrupts: Device sends interrupt to CPU•Cause identifies the interrupting device•interrupt handler examines device, decides what to doPriority interrupts•Urgent events can interrupt lower-priority interrupt handling•OS can disable defer interrupts21Typical x86 PC I/O System22I/O Data TransferHow to talk to device? Programmed I/O or Memory-Mapped I/OHow to get events?Polling or InterruptsHow to transfer lots of data?disk->cmd = READ_4K_SECTOR;disk->data = 12;while (!(disk->status & 1) { }for (i = 0..4k) buf[i] = disk->data;23DMA: Direct Memory AccessProgrammed I/O xfer: Device CPU RAMfor (i = 1 .. n)•CPU issues read request•Device puts data on bus& CPU reads into registers•CPU writes data to memoryCPU RAMDISK24I/O Data TransferQ: How to transfer lots of data efficiently?A: Have device access memory directlyDirect memory access (DMA)•OS provides starting address, length•controller (or device) transfers data autonomously•Interrupt on completion / error25DMA: Direct Memory AccessProgrammed I/O xfer: Device CPU RAMfor (i = 1 .. n)•CPU issues read request•Device puts data on bus& CPU reads into registers•CPU writes data to memoryDMA xfer: Device RAM•CPU sets up DMA request•for (i = 1 ... n)Device puts data on bus& RAM accepts itCPU RAMDISKCPU RAMDISK26DMA ExampleDMA example: reading from audio (mic) input•DMA engine on audio device… or I/O controller … or …int dma_size = 4*PAGE_SIZE;int *buf = alloc_dma(dma_size);...dev->mic_dma_baseaddr = (int)buf;dev->mic_dma_count = dma_len;dev->cmd = DEV_MIC_INPUT |DEV_INTERRUPT_ENABLE | DEV_DMA_ENABLE;27DMA Issues (1): AddressingIssue #1: DMA meets Virtual
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