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CORNELL CS 3410 - Virtual Memory 3

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Slide 1AnnouncementsGoals for TodaySlide 4Translation Lookaside Buffer (TLB)TLB DiagramA TLB in the Memory HierarchyTLB CoherencyTranslation Lookaside Buffers (TLBs)TLB ParametersSlide 11Virtually Addressed CachingVirtual vs. Physical CachesIndexing vs. TaggingTypical Cache SetupCaches/TLBs/VMSummary of Cache Design ParametersVirtual Memory 3Hakim WeatherspoonCS 3410, Spring 2011Computer ScienceCornell UniversityP & H Chapter 5.4-52AnnouncementsPA3 available. Due Tuesday, April 19th•Work with pairs•Be responsible with new knowledge•Scheduling a games night, possibly Friday, April 22nd Next four weeks•Two projects and one homeworks•Prelim2 will be Thursday, April 28th •PA4 will be final project (no final exam)–Will not be able to use slip days3Goals for TodayVirtual Memory•Address Translation•Pages, page tables, and memory mgmt unit•Paging•Role of Operating System•Context switches, working set, shared memory•Performance•How slow is it•Making virtual memory fast•Translation lookaside buffer (TLB)•Virtual Memory Meets Caching4Making Virtual Memory FastThe Translation Lookaside Buffer (TLB)5Translation Lookaside Buffer (TLB)Hardware Translation Lookaside Buffer (TLB)A small, very fast cache of recent address mappings•TLB hit: avoids PageTable lookup•TLB miss: do PageTable lookup, cache result for later6TLB DiagramV R W X D0 invalid1 00 invalid0 invalid1 00 01 10 invalidV R W X D tag ppnV0 invalid0 invalid0 invalid10 invalid110 invalid7A TLB in the Memory Hierarchy(1) Check TLB for vaddr (~ 1 cycle)(2) TLB Miss: traverse PageTables for vaddr(3a) PageTable has valid entry for in-memory page•Load PageTable entry into TLB; try again (tens of cycles)(3b) PageTable has entry for swapped-out (on-disk) page•Page Fault: load from disk, fix PageTable, try again (millions of cycles)(3c) PageTable has invalid entry•Page Fault: kill processCPUTLBLookupCacheMemDiskPageTableLookup(2) TLB Hit•compute paddr, send to cache8TLB CoherencyTLB Coherency: What can go wrong?A: PageTable or PageDir contents change•swapping/paging activity, new shared pages, …A: Page Table Base Register changes•context switch between processes9Translation Lookaside Buffers (TLBs)When PTE changes, PDE changes, PTBR changes….Full Transparency: TLB coherency in hardware•Flush TLB whenever PTBR register changes [easy – why?]•Invalidate entries whenever PTE or PDE changes [hard – why?]TLB coherency in softwareIf TLB has a no-write policy…•OS invalidates entry after OS modifies page tables•OS flushes TLB whenever OS does context switch10TLB ParametersTLB parameters (typical)•very small (64 – 256 entries), so very fast•fully associative, or at least set associative•tiny block size: why?Intel Nehalem TLB (example)•128-entry L1 Instruction TLB, 4-way LRU•64-entry L1 Data TLB, 4-way LRU•512-entry L2 Unified TLB, 4-way LRU11Virtual Memory meets CachingVirtually vs. physically addressed cachesVirtually vs. physically tagged caches12Virtually Addressed CachingQ: Can we remove the TLB from the critical path?A: Virtually-Addressed CachesCPUTLBLookupVirtuallyAddressedCacheMemDiskPageTableLookup13Virtual vs. Physical CachesCPUCacheSRAMMemoryDRAMaddrdataMMUCacheSRAMMMUCPUMemoryDRAMaddrdataCache works on physical addressesCache works on virtual addressesQ: What happens on context switch?Q: What about virtual memory aliasing?Q: So what’s wrong with physically addressed caches?14Indexing vs. TaggingPhysically-Addressed Cache•slow: requires TLB (and maybe PageTable) lookup firstVirtually-Indexed, Virtually Tagged Cache•fast: start TLB lookup before cache lookup finishes•PageTable changes (paging, context switch, etc.)  need to purge stale cache lines (how?)•Synonyms (two virtual mappings for one physical page) could end up in cache twice (very bad!)Virtually-Indexed, Physically Tagged Cache•~fast: TLB lookup in parallel with cache lookup•PageTable changes  no problem: phys. tag mismatch•Synonyms  search and evict lines with same phys. tagVirtually-Addressed Cache15Typical Cache SetupCPUL2 CacheSRAMMemoryDRAMaddrdataMMUTypical L1: On-chip virtually addressed, physically taggedTypical L2: On-chip physically addressedTypical L3: On-chip … L1 CacheSRAMTLB SRAM16Caches/TLBs/VMCaches, Virtual Memory, & TLBsWhere can block be placed?•Direct, n-way, fully associativeWhat block is replaced on miss?•LRU, Random, LFU, … How are writes handled?•No-write (w/ or w/o automatic invalidation)•Write-back (fast, block at time)•Write-through (simple, reason about consistency)17Summary of Cache Design ParametersL1 Paged Memory TLBSize (blocks)1/4k to 4k 16k to 1M 64 to 4kSize (kB)16 to 64 1M to 4G 2 to 16Block size (B)16-64 4k to 64k 4-32Miss rates2%-5% 10-4 to 10-5% 0.01% to 2%Miss penalty10-25 10M-100M


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CORNELL CS 3410 - Virtual Memory 3

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