A Processor Hakim Weatherspoon CS 3410 Spring 2010 Computer Science Cornell University See P H Chapter 2 16 20 4 1 3 Announcements HW2 available later today HW2 due in one week and a half Work alone Use your resources FAQ class notes book SecKons o ce hours newsgroup CSUGLab Make sure you Registered for class can access CMS have a SecKon and have a project partner Check online syllabus schedule review slides and lecture notes O ce Hours early homework and programming assignments 2 Announcements Prelims Evening of Thursday March 10 and April 28th Late Policy 1 Each person has a total of four slip days 2 For projects slip days are deducted from all partners 3 10 deducted per day late a er slip days are exhausted 3 Basic Computer System Let s build a MIPS CPU but using modi ed Harvard architecture Registers ALU CPU Control data address control 10100010000 10110000011 00100010101 00100000001 00100000010 00010000100 Data Memory Program Memory 4 Instructions High Level Language C Java Python Ruby Loops control ow variables for i 0 i 10 i printf go cucs main addi r2 r0 10 addi r1 r0 0 loop slt r3 r1 r2 00100000000000100000000000001010 00100000000000010000000000000000 00000000001000100001100000101010 Assembly Language No symbols except labels One operaKon per statement Machine Langauge Binary encoded assembly Labels become addresses 5 Instruction Types ArithmeKc add subtract shi le shi right mulKply divide Memory load value from memory to a register store value to memory from a register Control ow uncondiKonal jumps condiKonal jumps branches jump and link subrouKne call Many other instrucKons are possible vector add sub mul div string operaKons manipulate coprocessor I O 6 Complexity MIPS Reduced InstrucKon Set Computer RlSC 200 instrucKons 32 bits each 3 formats mostly orthogonal all operands in registers almost all are 32 bits each can be used interchangeably 1 addressing mode Mem reg imm x86 Complex InstrucKon Set Computer ClSC 1000 instrucKons 1 to 15 bytes each operands in special registers general purpose registers memory on stack can be 1 2 4 8 bytes signed or unsigned 10s of addressing modes e g Mem segment reg reg scale o set 7 MIPS Register file MIPS register le 32 registers 32 bits each with r0 wired to zero Write port indexed via RW Writes occur on falling edge but only if WE is high Read ports indexed via RA RB W 32 clk r1 r2 r31 5 32 A 32 B 5 WE RW RA 5 RB 8 MIPS Memory MIPS Memory Up to 32 bit address 32 32 bit data but byte addressed Enable 2 bit memory control 00 read word 4 byte aligned 01 write byte 10 write halfword 2 byte aligned 11 write word 4 byte aligned memory 32 2 addr mc 32 E 9 Instruction Usage Basic CPU execuKon loop 1 2 3 4 fetch one instrucKon increment PC decode execute 10 Instruction Fetch InstrucKon Fetch Circuit Fetch instrucKon from memory Calculate address of next instrucKon Repeat Program inst 32 Memory 32 2 00 4 PC 11 Arithmetic Instructions 00000001000001100010000000100110 op 6 bits op 0x0 0x0 0x0 0x0 0x0 rs rt 5 bits 5 bits func 0x21 0x23 0x25 0x26 0x27 rd func 5 bits 5 bits 6 bits mnemonic ADDU rd rs rt SUBU rd rs rt OR rd rs rt XOR rd rs rt NOR rd rs rt R Type description R rd R rs R rt R rd R rs R rt R rd R rs R rt R rd R rs R rt R rd R rs R rt 12 Arithmetic and Logic Prog inst Mem Reg File ALU 4 PC 5 5 5 control 13 Example Programs r4 r1 r2 r3 r8 4 r3 r4 1 r9 9 ADDU rd rs rt SUBU rd rs rt OR rd rs rt XOR rd rs rt NOR rd rs rt 14 InstrucKon fetch decode ALU Babbage s engine speed reliability hand crank 15 Arithmetic Instructions Shift 00000000000001000100000110000011 op 6 bits op 0x0 0x0 0x0 func 0x0 0x2 0x3 rt 5 bits 5 bits rd shamt func 5 bits mnemonic SLL rd rs shamt SRL rd rs shamt SRA rd rs shamt 5 bits R Type 6 bits description R rd R rt shamt R rd R rt shamt zero ext R rd R rs shamt sign ext ex r5 r3 8 16 Shift Prog inst Mem Reg File ALU 4 5 5 5 PC shamt control 17 Arithmetic Instructions Immediates 00100100101001010000000000000101 op 6 bits op 0x9 0xc 0xd rs rd immediate 5 bits 5 bits mnemonic ADDIU rd rs imm ANDI rd rs imm ORI rd rs imm ex r5 5 I Type 16 bits description R rd R rs simm ign extend imm R rd R rs zimm ero extend imm R rd R rs zimm ero extend imm ex r9 1 ex r9 65535 18 Immediates Prog inst Mem ALU Reg File 4 5 5 5 PC control control imm extend shamt 19 Arithmetic Instructions Immediates 00111100000001010000000000000101 op 6 bits op 0xF rd 5 bits 5 bits mnemonic LUI rd imm immediate I Type 16 bits description R rd imm 16 ex r5 0xdeadbeef 20 Immediates Prog inst Mem ALU Reg File 4 5 5 5 PC control control imm 16 extend shamt 21 MIPS Instruction Types ArithmeKc Logical R type result and two source registers shi amount I type 16 bit immediate with sign zero extension Memory Access load store between registers and memory word half word and byte operaKons Control ow condiKonal branches pc relaKve addresses jumps xed o sets register absolute 22 Memory Instructions 10100100101000010000000000000010 op 6 bits op 0x20 0x24 0x21 0x25 0x23 0x28 0x29 0x2b rs rd 5 bits 5 bits mnemonic LB rd o set rs LBU rd o set rs LH rd o set rs LHU rd o set rs LW rd o set rs SB rd o set rs SH rd o set rs SW rd o set rs offset 16 bits I Type base o set addressing description R rd sign ext Mem o set R rs R rd zero ext Mem o set R rs R rd sign ext Mem o set R rs R rd zero ext Mem o set R rs R rd Mem o set R rs signed Mem o set R rs R rd o sets Mem o set R rs R rd Mem o set R rs R rd 23 Memory Operations Prog inst Mem ALU Reg File 4 addr 5 5 5 PC Data Mem control imm ext 24 Example int h A A 12 h A 8 25 Memory Layout Examples r5 contains 0x5 sb r5 2 r0 lb r6 2 r0 sw r5 8 r0 lb r7 8 r0 lb r8 11 r0 0x00000000 0x00000001 0x00000002 0x00000003 0x00000004 0x00000005 0x00000006 0x00000007 0x00000008 0x00000009 0x0000000a 0x0000000b 0xffffffff 26 Endianness Endianness Ordering of bytes within a memory word Li le Endian least signi cant part rst MIPS x86 1000 1001 1002 1003 as 4 bytes as 2 halfwords as 1 word 0x12345678 Big Endian most signi cant part rst MIPS networks 1000 1001 1002 1003 as 4 bytes as 2 halfwords as 1 word 0x12345678 27 Control Flow Absolute …
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