CORNELL CS 3410 - Study Notes (61 pages)

Previewing pages 1, 2, 3, 4, 28, 29, 30, 31, 58, 59, 60, 61 of 61 page document View the full content.
View Full Document

Study Notes



Previewing pages 1, 2, 3, 4, 28, 29, 30, 31, 58, 59, 60, 61 of actual document.

View the full content.
View Full Document
View Full Document

Study Notes

55 views


Pages:
61
School:
Cornell University
Course:
Cs 3410 - Computer System Organization and Programming
Computer System Organization and Programming Documents

Unformatted text preview:

Virtual Memory 1 Hakim Weatherspoon CS 3410 Spring 2011 Computer Science Cornell University P H Chapter 5 4 up to TLBs Announcements HW3 available due today Tuesday HW3 has been updated Use updated version Work with alone Be responsible with new knowledge PA3 available later today or by tomorrow Work in pairs Next ve weeks One homeworks and two projects Prelim2 will be Thursday April 28th PA4 will be nal project no nal exam 2 Goals for Today Title says Virtual Memory but really nish caches writes Introduce idea of Virtual Memory 3 Cache Design Need to determine parameters Cache size Block size aka line size Number of ways of set associaWvity 1 N EvicWon policy Number of levels of caching parameters for each Separate I cache from D cache or Uni ed cache Prefetching policies instrucWons Write policy 4 A Real Example dmidecode t cache Cache Information Configuration Enabled Not Socketed Level 1 Operational Mode Write Back Installed Size 128 KB Error Correction Type None Cache Information Configuration Enabled Not Socketed Level 2 Operational Mode Varies With Memory Address Installed Size 6144 KB Error Correction Type Single bit ECC cd sys devices system cpu cpu0 grep cache cache index0 level 1 cache index0 type Data cache index0 ways of associativity 8 cache index0 number of sets 64 cache index0 coherency line size 64 cache index0 size 32K cache index1 level 1 cache index1 type Instruction cache index1 ways of associativity 8 cache index1 number of sets 64 cache index1 coherency line size 64 cache index1 size 32K cache index2 level 2 cache index2 type Unified cache index2 shared cpu list 0 1 cache index2 ways of associativity 24 cache index2 number of sets 4096 cache index2 coherency line size 64 cache index2 size 6144K Dual core 3 16GHz Intel purchased in 2009 5 A Real Example Dual 32K L1 InstrucWon caches 8 way set associaWve 64 sets 64 byte line size Dual core 3 16GHz Intel purchased in 2009 Dual 32K L1 Data caches Same as above Single 6M L2 Uni ed cache 24 way set



View Full Document

Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Study Notes and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Study Notes and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?