Slide 1AnnouncementsAnnouncementsBasic Computer SystemInstructionsInstruction TypesComplexityMIPS Register fileMIPS MemoryInstruction UsageInstruction FetchArithmetic InstructionsArithmetic and LogicExample ProgramsSlide 15Arithmetic Instructions: ShiftShiftArithmetic Instructions: ImmediatesImmediatesArithmetic Instructions: ImmediatesImmediatesMIPS Instruction TypesMemory InstructionsMemory OperationsExampleMemory LayoutEndiannessControl Flow: Absolute JumpAbsolute JumpControl Flow: Jump RegisterJump RegisterExamples (2)Examples (2)Examples (2)Control Flow: BranchesExamples (3)Absolute JumpAbsolute JumpControl Flow: More BranchesAbsolute JumpControl Flow: Jump and LinkAbsolute JumpNext TimeHakim WeatherspoonCS 3410, Spring 2010Computer ScienceCornell UniversityA ProcessorSee: P&H Chapter 2.16-20, 4.1-32AnnouncementsHW2 available later todayHW2 due in one week and a halfWork aloneUse your resources•FAQ, class notes, book, Sections, office hours, newsgroup, CSUGLabMake sure you•Registered for class, can access CMS, have a Section, and have a project partner•Check online syllabus/schedule, review slides and lecture notes, Office Hours, early homework and programming assignments3AnnouncementsPrelims: Evening of Thursday, March 10 and April 28thLate Policy1) Each person has a total of four “slip days”2) For projects, slip days are deducted from all partners 3) 10% deducted per day late after slip days are exhausted4Basic Computer SystemLet’s build a MIPS CPU•…but using (modified) Harvard architectureCPURegistersDataMemorydata, address, controlALUControl001000000010010000001000010000100...ProgramMemory101000100001011000001100100010101...5InstructionsHigh Level Language•C, Java, Python, Ruby, …•Loops, control flow, variablesfor (i = 0; i < 10; i++)printf(“go cucs”); main: addi r2, r0, 10addi r1, r0, 0 loop: slt r3, r1, r2...001000000000001000000000000010100010000000000001000000000000000000000000001000100001100000101010Assembly Language•No symbols (except labels)•One operation per statementMachine Langauge•Binary-encoded assembly•Labels become addresses6Instruction TypesArithmetic•add, subtract, shift left, shift right, multiply, divideMemory•load value from memory to a register•store value to memory from a registerControl flow•unconditional jumps•conditional jumps (branches)•jump and link (subroutine call)Many other instructions are possible•vector add/sub/mul/div, string operations •manipulate coprocessor•I/O7ComplexityMIPS•≈ 200 instructions, 32 bits each, 3 formats–mostly orthogonal•all operands in registers–almost all are 32 bits each, can be used interchangeably•≈ 1 addressing mode: Mem[reg + imm]x86 = Complex Instruction Set Computer (ClSC)•> 1000 instructions, 1 to 15 bytes each•operands in special registers, general purpose registers, memory, on stack, …–can be 1, 2, 4, 8 bytes, signed or unsigned•10s of addressing modes–e.g. Mem[segment + reg + reg*scale + offset]= Reduced Instruction Set Computer (RlSC)8MIPS Register fileMIPS register file•32 registers, 32-bits each (with r0 wired to zero)•Write port indexed via RW–Writes occur on falling edgebut only if WE is high•Read ports indexed via RA, RBclkW32ABr1r2…r31555WE RWRARB32329MIPS MemoryMIPS Memory•Up to 32-bit address•32-bit data(but byte addressed)•Enable + 2 bit memory control00: read word (4 byte aligned)01: write byte10: write halfword (2 byte aligned)11: write word (4 byte aligned)memory≤ 32addr2mc32 32E10Instruction UsageBasic CPU execution loop1. fetch one instruction2. increment PC3. decode 4. execute11Instruction FetchInstruction Fetch Circuit•Fetch instruction from memory•Calculate address of next instruction•RepeatProgramMemory inst32PC20032+412Arithmetic Instructionsop rs rt rd - func6 bits 5 bits 5 bits 5 bits 5 bits 6 bitsop func mnemonic description0x0 0x21 ADDU rd, rs, rt R[rd] = R[rs] + R[rt]0x0 0x23 SUBU rd, rs, rt R[rd] = R[rs] – R[rt]0x0 0x25 OR rd, rs, rt R[rd] = R[rs] | R[rt]0x0 0x26 XOR rd, rs, rtR[rd] = R[rs] R[rt]0x0 0x27 NOR rd, rs rt R[rd] = ~ ( R[rs] | R[rt] )00000001000001100010000000100110R-Type13Arithmetic and Logic5ALU5 5controlReg.FilePCProg.Meminst+414Example Programsr4 = (r1 + r2) | r3r8 = 4*r3 + r4 – 1r9 = 9ADDU rd, rs, rtSUBU rd, rs, rtOR rd, rs, rtXOR rd, rs, rtNOR rd, rs rt15Instruction fetch + decode + ALU= Babbage’s engine + speed + reliability – hand crank16Arithmetic Instructions: Shiftop - rt rd shamtfunc6 bits 5 bits 5 bits 5 bits 5 bits 6 bitsop func mnemonic description0x0 0x0 SLL rd, rs, shamt R[rd] = R[rt] << shamt0x0 0x2 SRL rd, rs, shamt R[rd] = R[rt] >>> shamt (zero ext.)0x0 0x3 SRA rd, rs, shamt R[rd] = R[rs] >> shamt (sign ext.)00000000000001000100000110000011ex: r5 = r3 * 8R-Type17Shift5ALU5 5controlReg.FilePCProg.Meminst+4shamt18op mnemonic description0x9 ADDIU rd, rs, imm R[rd] = R[rs] + imm0xc ANDI rd, rs, imm R[rd] = R[rs] & imm0xd ORI rd, rs, imm R[rd] = R[rs] | immArithmetic Instructions: Immediatesop mnemonic description0x9 ADDIU rd, rs, imm R[rd] = R[rs] + sign_extend(imm)0xc ANDI rd, rs, imm R[rd] = R[rs] & zero_extend(imm)0xd ORI rd, rs, imm R[rd] = R[rs] | zero_extend(imm)op rs rd immediate6 bits 5 bits 5 bits 16 bits00100100101001010000000000000101I-Typeex: r5 += 5ex: r9 = -1 ex: r9 = 6553519Immediates5imm5 5controlextend+4shamtcontrolReg.FilePCProg.MemALUinst20Arithmetic Instructions: Immediatesop mnemonic description0xF LUI rd, imm R[rd] = imm << 16op - rd immediate6 bits 5 bits 5 bits 16 bits00111100000001010000000000000101I-Typeex: r5 = 0xdeadbeef21Immediates5imm5 5controlextend+4shamtcontrolReg.FilePCProg.MemALUinst1622MIPS Instruction TypesArithmetic/Logical•R-type: result and two source registers, shift amount•I-type: 16-bit immediate with sign/zero extensionMemory Access•load/store between registers and memory•word, half-word and byte operationsControl flow•conditional branches: pc-relative addresses•jumps: fixed offsets, register absolute23Memory Instructionsop mnemonic description0x20 LB rd, offset(rs) R[rd] = sign_ext(Mem[offset+R[rs]])0x24 LBU rd, offset(rs) R[rd] = zero_ext(Mem[offset+R[rs]])0x21 LH rd, offset(rs) R[rd] = sign_ext(Mem[offset+R[rs]])0x25 LHU rd, offset(rs) R[rd] = zero_ext(Mem[offset+R[rs]])0x23 LW rd, offset(rs) R[rd] = Mem[offset+R[rs]]0x28 SB rd, offset(rs) Mem[offset+R[rs]] = R[rd]0x29 SH rd, offset(rs) Mem[offset+R[rs]] = R[rd]0x2b SW rd, offset(rs) Mem[offset+R[rs]] = R[rd]op rs rd offset6
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