UCLA COMSCI M151B - Lecture10 (7 pages)

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Lecture10



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Lecture10

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Pages:
7
School:
University of California, Los Angeles
Course:
Comsci M151b - Computer Systems Architecture
Computer Systems Architecture Documents

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Week 6 Wednesday 4 8 Hazards Performance will drop CPI will be above 1 0 in the ideal case Three types of hazards Data hazards Data is incorrect Control hazards Control is incorrect Structure hazards Resource utilization that won t work out Example of Data Hazard add 3 10 11 R 10 20 R 11 22 R 3 6 This should add 20 22 putting result 42 into 3 Takes register values in R 10 and R 11 and put it into R 3 lw 8 50 3 This should load memory location R 3 added 50 into R 8 sub 11 8 7 R 7 14 This should subtract 14 from that just loaded value Takes register values in R 8 and R 7 and put it into R 11 These 3 instructions are considered in a straight lined chain dependencies Load word uses register value from add Subtract uses register value from load word Instructions uses register value from previous instructions The Pipeline in Execution IF sub 11 8 7 ID lw 8 50 3 EX add 3 10 11 MEM none WB none HAZARD At ID stage R 3 should have been 42 but instead it s still 6 It wasn t updated yet because add is still in execution IF add 10 1 2 ID sub 11 8 7 EX lw 8 50 3 MEM add 3 10 11 WB none HAZARD At ID stage R 8 should have been a value loaded from M 92 but instead it s still loading from M 16 It wasn t updated yet because lw is still in execution One instruction that depends on another instruction reads an incorrect data value because it hasn t been written Hazard continued Situations that prevent starting the next instruction in the next cycle Structure hazards A required resource is busy Multiple instructions going through a pipeline at the same time Both instructions need to make a use of the data port memory But we only have a single data port One instruction has to wait for one another Data hazard Need to wait for previous instruction to compete its data read write Control hazard Deciding on control action depends on previous instruction Wait on a branch to resolve to know what our current PC should be Structure Hazards Conflict for use of a resource In MIPS pipeline with a



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