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UCLA COMSCI M151B - !2004 HW05_Answers

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1) (5 pts) Segmentation is a memory management scheme that does not reflect the programmer’s view of memory?2) (5 pts) Segmentation looks similar to contiguous allocation with multiple dynamic partitions if an entire program is treated as a single segment.3) (5 pts) Segmentation requires which of the following:4) (10 pts) Small page tables (and segment tables) can be kept in fast registers for quick reference. If the number of pages for a particular process is large, the page table must be stored in memory. Assuming a page table is in memory and there is no TLB, how many memory accesses are required for each logical address referenced? What is retrieved during each access?5) (10 pts) A process has associated with it the following table. For each logical address shown indicate if the address is legal. If it is, compute the physical address. Addresses are in the form <p, d>. Assume each page/frame is 1000 bytes in size.6) (10 pts) The same page table as the previous problem. What happens when the size of the page is increased to 4000 bytes per page?7) (20 pts) Consider a system using paging with page tables for each process stored in main memory.8) (10 pts) List four additional hardware and software components necessary to make paging work in a computer system.9) (15 pts) For this problem, assume we are working with a decimal (base 10) computer. Given a paged memory system where:each page contains 100 bytes (102),the physical memory contains a total of 1,000,000 bytes (106), andlogical memory (a program’s maximum logical address space) consists of 10,000 bytes (104).10) (5 pts) Pointers to page tables are kept where? ___________in a process’ PCB____________11) (5 pts) If paging is so complicated to implement, why do we bother with it?Operating System ConceptsCGS 3763, Spring 2004Homework Assignment #5Due Wednesday, April 14th Name _________________(at beginning of class)Please read the following certification and sign where indicated:I hereby certify that the answers I am submitting for this homework assignment are my own and that I have not obtained answers from any other student. I also certify that I have not provided my answers to any other student to copy or use as the basis for his/her homework. I understand that cheating on this or any other assignment or test will immediately result in a score of “0” for the assignment in addition to possible disciplinary action by the University. I also acknowledge that I have read and understand the University’s policies regarding “Student Academic Behavior”as provided at www.ucf.edu/goldenrule._________________________________ Student Signature1) (5 pts) Segmentation is a memory management scheme that does not reflect the programmer’s view of memory?TRUE FALSE2) (5 pts) Segmentation looks similar to contiguous allocation with multiple dynamic partitions if an entire program is treated as a single segment.TRUE FALSE3) (5 pts) Segmentation requires which of the following:a. Unique hardware for address translationb. Special compilers to divide programs into segments and generate two-tuple logical addresses (<segment, offset>).c. The ability for the OS to track free space in the system (e.g., free space table)d. External fragments to keep the segments separated.e. none of the above.4) (10 pts) Small page tables (and segment tables) can be kept in fast registers for quick reference. If the number of pages for a particular process is large, the page table must be stored in memory. Assuming a page table is in memory and there is no TLB, how many memory accessesare required for each logical address referenced? What is retrieved during each access?Two (2) memory accesses are required for each referenced logical address:1) The first access retrieves the page table entry (frame).2) After computing the physical address (frame + offset), the second access retrieves the actual data or instruction required by the program5) (10 pts) A process has associated with it the following table. For each logical address shown indicate if the address is legal. If it is, compute the physical address. Addresses are in the form <p, d>. Assume each page/frame is 1000 bytes in size.Page # Frame #0 241 142 63 55Logical Address < 0, 321 > Is it legal? ___Y___ Physical Address ___24321____(24 * 1000 + 321)Logical Address < 1, 3100 > Is it legal? ___N___ Physical Address ____________(Displacement of 6100 is greater than size of one page)Logical Address < 4, 754 > Is it legal? ___N___ Physical Address ____________(Page 4 is invalid. Does not appear in the page table)Logical Address < 2, 208 > Is it legal? ___Y___ Physical Address ___6208_____(6 * 1000 + 208)Logical Address < 3, 0 > Is it legal? ___Y___ Physical Address ___55000___(55 * 1000 + 0)6) (10 pts) The same page table as the previous problem. What happens when the size of the page is increased to 4000 bytes per page?Logical Address < 0, 321 > Is it legal? ___Y___ Physical Address ___96,321_____(24 * 4000 + 321)Logical Address < 1, 3100 > Is it legal? ___Y___ Physical Address ___59,100______(14 * 4000 + 321)Logical Address < 4, 754 > Is it legal? ___N___ Physical Address ____________(Page 4 is invalid. Does not appear in the page table)Logical Address < 2, 208 > Is it legal? ___Y___ Physical Address ___24,208_____(6 * 4000 + 208)Logical Address < 3, 0 > Is it legal? ___Y___ Physical Address ___220,000___(55 * 4000 + 0)7) (20 pts) Consider a system using paging with page tables for each process stored in main memory. If a single memory reference takes 150 nanoseconds, how long does a paged memory reference take?Each memory reference requires two (2) memory accesses if process page tables are stored in memory. The first reference fetches the page table entry (page #, frame address, valid/invalid bit). Address translation hardware computes the physical address (frame address + page offset). Then the second memory access fetches the data or instruction required by the program.150 nanoseconds x 2 = 300 nanosecondsIf we add associative registers (aka TLBs) and 90% of all page-table references are found in the associative registers, what is the effective memory access time? Assume that finding a page-table entry in the TLB takes 10 nanoseconds.Time for memory reference if page-table entry in TLB: Check TLB + fetch data/instruction = 10 + 150 = 160 nanosecondsTime for memory reference if page-table entry (PTE) not in TLB: Check TLB + fetch


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UCLA COMSCI M151B - !2004 HW05_Answers

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