SOLUTIONS MANUALCOMPUTER ORGANIZATION ANDARCHITECTUREDESIGNING FOR PERFORMANCESEVENTH EDITIONWILLIAM STALLINGSCopyright 2005: William Stallings-2-© 2005 by William StallingsAll rights reserved. No part of this document maybe reproduced, in any form or by any means, orposted on the Internet, without permission inwriting from the author.-3-NOTICEThis manual contains solutions to all of the review questions andhomework problems in Computer Organization and Architecture,Seventh Edition. If you spot an error in a solution or in the wording of aproblem, I would greatly appreciate it if you would forward theinformation via email to [email protected]. An errata sheet for this manual,if needed, is available at WilliamStallings.comW.S.-4-TABLE OF CONTENTSChapter 2: Computer Evolution and Performance.....................................................5Chapter 3: Computer Function and Interconnection.................................................9Chapter 4: Cache Memory............................................................................................14Chapter 5: Internal Memory........................................................................................27Chapter 6: External Memory........................................................................................33Chapter 7: Input/Output.............................................................................................37Chapter 8: Operating System Support.......................................................................43Chapter 9: Computer Arithmetic................................................................................48Chapter 10: Instruction Sets: Characteristics and Functions.....................................61Chapter 11: Instruction Sets: Addressing Modes and Formats................................72Chapter 12: Processor Structure and Function............................................................77Chapter 13: Reduced Instruction Set Computers (RISCs).........................................83Chapter 14: Instruction-Level Parallelism and Superscalar Processors..................87Chapter 15: The IA-64 Architecture..............................................................................93Chapter 16: Control Unit Operation.............................................................................97Chapter 17: Microprogrammed Control....................................................................100Chapter 18: Parallel Processing...................................................................................103Appendix A: Number Systems......................................................................................112Appendix B: Digital Logic..............................................................................................113-5-AANSWERS TO NSWERS TO QQUESTIONSUESTIONS2.1 In a stored program computer, programs are represented in a form suitable forstoring in memory alongside the data. The computer gets its instructions by readingthem from memory, and a program can be set or altered by setting the values of aportion of memory.2.2 A main memory, which stores both data and instructions: an arithmetic and logicunit (ALU) capable of operating on binary data; a control unit, which interprets theinstructions in memory and causes them to be executed; and input and output(I/O) equipment operated by the control unit.2.3 Gates, memory cells, and interconnections among gates and memory cells.2.4 Moore observed that the number of transistors that could be put on a single chipwas doubling every year and correctly predicted that this pace would continue intothe near future.2.5 Similar or identical instruction set: In many cases, the same set of machineinstructions is supported on all members of the family. Thus, a program thatexecutes on one machine will also execute on any other. Similar or identicaloperating system: The same basic operating system is available for all familymembers. Increasing speed: The rate of instruction execution increases in goingfrom lower to higher family members. Increasing Number of I/O ports: In goingfrom lower to higher family members. Increasing memory size: In going fromlower to higher family members. Increasing cost: In going from lower to higherfamily members.2.6 In a microprocessor, all of the components of the CPU are on a single chip.AANSWERS TO NSWERS TO PPROBLEMSROBLEMS2.1 This program is developed in [HAYE98]. The vectors A, B, and C are each stored in1,000 contiguous locations in memory, beginning at locations 1001, 2001, and 3001,respectively. The program begins with the left half of location 3. A countingvariable N is set to 999 and decremented after each step until it reaches –1. Thus,the vectors are processed from high location to low location.CHAPTER 2COMPUTER EVOLUTION ANDPERFORMANCE-6-LocationInstructionComments0999Constant (count N)11Constant21000Constant3LLOAD M(2000)Transfer A(I) to AC3RADD M(3000)Compute A(I) + B(I)4LSTOR M(4000)Transfer sum to C(I)4RLOAD M(0)Load count N5LSUB M(1)Decrement N by 15RJUMP+ M(6, 20:39)Test N and branch to 6R if nonnegative6LJUMP M(6, 0:19)Halt6RSTOR M(0)Update N7LADD M(1)Increment AC by 17RADD M(2)8LSTOR M(3, 8:19)Modify address in 3L8RADD M(2)9LSTOR M(3, 28:39)Modify address in 3R9RADD M(2)10LSTOR M(4, 8:19)Modify address in 4L10RJUMP M(3, 0:19)Branch to 3L2.2 a.OpcodeOperand00000001000000000010b. First, the CPU must make access memory to fetch the instruction. Theinstruction contains the address of the data we want to load. During the executephase accesses memory to load the data value located at that address for a totalof two trips to memory.2.3 To read a value from memory, the CPU puts the address of the value it wants intothe MAR. The CPU then asserts the Read control line to memory and places theaddress on the address bus. Memory places the contents of the memory locationpassed on the data bus. This data is then transferred to the MBR. To write a value tomemory, the CPU puts the address of the value it wants to write into the MAR. TheCPU also places the data it wants to write into the MBR. The CPU then asserts theWrite control line to memory and places the address on the address bus and thedata on the data bus. Memory transfers the data on the data bus into thecorresponding memory location.-7-2.4AddressContents08A08B08C08DLOAD M(0FA)STOR M(0FB)LOAD M(0FA)JUMP +M(08D)LOAD –M(0FA)STOR M(0FB)This program will store the absolute value of content at memory location 0FA