Page 1Last Updated: November 2003Chapter 6 Instructor's Manual______________________________________________________________________________Chapter ObjectivesChapter 6, Memory, covers basic memory concepts, such as RAM and the various memorydevices, and also addresses the more advanced concepts of the memory hierarchy, includingcache memory and virtual memory. This chapter gives a thorough presentation of directmapping, associative mapping, and set-associative mapping techniques for cache. It alsoprovides a detailed look at overlays, paging and segmentation, TLBs, and the variousalgorithms and devices associated with each. A tutorial and simulator for this chapter isavailable.Lectures should focus on the following points:• Types of memory. There are many types of memory, but the two basic categories are RAMand ROM.• The memory hierarchy. One of the most important considerations in understanding theperformance capabilities of a modern computer is the memory hierarchy. The goal of thissection is understanding how system memory (registers, cache, and main memory), onlinememory (hard disk), near line memory (optical disk), and offline memory (tapes and floppydisks) work together to provide acceptable performance at a minimal cost. Locality ofreference (or the clustering of memory references) is integral in understanding how amemory hierarchy works.• Cache memory. The purpose of cache is to speed up memory accesses by storing recentlyused data closer to the CPU (in a memory that requires less access time). It is important todiscuss where this data is stored in cache, so direct mapping, fully associative cache, andset associative cache are covered. The effective access time is a good way to measure theperformance of cache.• Virtual memory. Virtual memory is a method used to increase the available address spacefor a process by using the hard disk as an extension of RAM. Both paging andsegmentation (including advantages and disadvantages) are covered. In addition TLBs areintroduced as a method for improving performance of paging systems.• Real-world examples of memory management. The chapter concepts are studied in thecontext of the Pentium memory hierarchy.The Essentials of Computer Organization and ArchitectureLinda Null and Julia LoburJones and Bartlett Publishers, 2003Page 2Last Updated: November 2003Required Lecture TimeThe important concepts in Chapter 6 can typically be covered in 5 lecture hours. However, if ateacher wants the students to have a mastery of all topics in Chapter 6, 9 lecture hours aremore reasonable. If lecture time is limited, we suggest that the focus be on the memoryhierarchy and cache memory. Virtual memory is often covered in an operating systems course,but we provide coverage in this textbook because we feel it is important that students see thehierarchy in its entirety.Lecture TipsStudents often have difficulty understanding why the memory hierarchy works. In particular,many miss the concept of bringing in an entire block when a "miss" occurs (thus using theprinciple of locality). Instructors should focus on several small examples to make surestudents understand the concept of locality. This will also help with the section on paging.Although the cache mapping schemes are relatively straight forward, students have a tendencyto miss why the schemes are necessary. (For example, many can work examples involving thevarious mapping schemes, but they aren't sure exactly what they are doing and why they aredoing it.) It is important to stress not only how the main memory address is mapped to a cachelocation but why.For the various cache mapping schemes, we have found that working out small examples indetail is a good way to approach these concepts. Examples showing blocks of memory actuallyput into a small cache, and then that cache getting full (or several blocks mapping to the samelocation in cache) are very helpful for motivating the need for the tag in cache.If students are comfortable with cache mapping, paging is much easier for them to deal with,as many concepts are similar. However, these similarities can cause confusion for thestudents, as some tend to mix up cache and paging. Covering examples using both cache andpaging helps to clear up this confusion.Answers to Exercises1. Suppose a computer using direct mapped cache has 220 words of main memory, and acache of 32 blocks, where each cache block contains 16 words.a. How many blocks of main memory are there?b. What is the format of a memory address as seen by the cache, i.e., what are the sizes ofthe tag, block, and word fields?c. To which cache block will the memory reference 0DB6316 map?Ans.a. 220/24 = 216b. 20 bit addresses with 11 bits in the tag field, 5 in the block field, and 4 in the word fieldc. 0DB63 = 00001100101 10110 0111, which implies Block 22______________________________________________________________________________2. Suppose a computer using direct mapped cache has 232 words of main memory, and acache of 1024 blocks, where each cache block contains 32 words.Page 3Last Updated: November 2003a. How many blocks of main memory are there?b. What is the format of a memory address as seen by the cache, i.e., what are the sizes ofthe tag, block, and word fields?c. To which cache block will the memory reference 000063FA16 map?Ans.a. 232/25 = 227b. 32 bit addresses with 17 bits in the tag field, 10 in the block field, and 5 in the wordfieldc. 000063FA = 00000000000000000 1100011111 11010, which implies Block 799______________________________________________________________________________3. Suppose a computer using fully associative cache has 216 words of main memory, and acache of 64 blocks, where each cache block contains 32 words.a. How many blocks of main memory are there?b. What is the format of a memory address as seen by the cache, i.e., what are the sizes ofthe tag and word fields?c. To which cache block will the memory reference F8C9 map?Ans.a. 216/25 = 211b. 16 bit addresses with 11 bits in the tag field and 5 in the word fieldc. Since it's associative cache, it can map anywhere______________________________________________________________________________4. Suppose a computer using fully associative cache has 224 words of main memory, and acache of 128 blocks, where each cache block contains 64 words.a. How many blocks of main memory are there?b. What is the format of a memory address as seen by the cache, i.e., what are the sizes ofthe tag and