Systems Architecture II (CS 282-001) Lecture 9: I/O Devices and Communication Buses *IntroductionInterfacing Processors and PeripheralsTypes and Characteristics of I/O DevicesMagnetic DiskDisk PerformanceSlide 7BusesBus ConfigurationsBus Input and OutputSynchronous vs. AsynchronousHandshaking ProtocolSlide 13FSM Control for Handshaking ProtocolPerformance ComparisonImproving Bus PerformancePerformance ExampleSlide 18Bus ArbitrationBus Arbitration (detail)Single Bus Master (Processor)Daisy Chain ArbitrationAugust 1, 2001 Systems Architecture II 1Systems Architecture II (CS 282-001) Lecture 9: I/O Devices and Communication Buses *Jeremy R. JohnsonWednesday, August 1, 2001*This lecture was derived from material in the text (Chap. 8). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).August 1, 2001 Systems Architecture II 2Introduction•Objective: To understand the basic principles of different I/O devices and to develop protocols for connecting I/O devices to processors and memory. To analyze and compare performance of I/O devices and communication protocols.•Topics–Design issues and importance of I/O–I/O devices•keyboard and monitor•mouse•magnetic disk•network–Buses•synchronous vs. asynchronous•handshaking protocol•bus arbitrationAugust 1, 2001 Systems Architecture II 3Interfacing Processors and Peripherals•Design Issues:–performance–resilience–expandability–different devices•Performance–access latency–throughput•transfer bandwidth•transfers per second•Interface–bus protocols–interruptsMainmemoryI/OcontrollerI/OcontrollerI/OcontrollerDiskGraphicsoutputNetworkMemory– I/O busProcessorCacheInterruptsDiskAugust 1, 2001 Systems Architecture II 4Types and Characteristics of I/O Devices•Diverse devices–Behavior (input vs. output)–Partner (human vs. machine)–data rateDevice Behavior Partner Data rate (KB/sec)Keyboard input human 0.01Mouse input human 0.02Voice input input human 0.02Scanner input human 400.00Voice output output human 0.60Line printer output human 1.00Laser printer output human 200.00Graphics display output human 60,000.00Modem input or output machine 2.00-8.00Network/LAN input or output machine 500.00-6000.00Floppy disk storage machine 100.00Optical disk storage machine 1000.00Magnetic tape storage machine 2000.00Magnetic disk storage machine 2000.00-10,000.00August 1, 2001 Systems Architecture II 5Magnetic Disk•Rotating disk with magnetic surface–3600 to 10,000 RPM–$0.10 per MB•hard disk organized into platters•each surface made up of tracks–1000-5000•tracks divided into sectors–64-200–512 bytes per sectorPlatterTrackPlattersSectorsTracksAugust 1, 2001 Systems Architecture II 6Disk Performance•Average disk access time =–avg. seek time + avg. rotational delay + transfer time + controller overhead•Avg. seek time (time to move head to track)–may be 25% of manufacturer reported time due to locality•Avg. rotational delay–0.5 rotation/RPM•Transfer time –depends on rotation speed, sector size, track density–caching used to improve transfer rate•What is the average time to read a 512-byte sector from a typical disk rotating at 5400 RPM?–Average seek time = 12ms–Transfer rate = 5 MB/sec–Controller overhead = 2msAugust 1, 2001 Systems Architecture II 7Disk Performance•Average seek time–12 ms (advertised - averaged over all possible seeks)–3 ms (measured typically 25% of advertised)•Average rotational delay–.5 rotation/5400 RPM = .5 rotation/(5400 RPM/60 sec/min) = 0.0056 sec = 5.6 ms•Transfer time–.5KB/(5MB/sec) = 0.0001 sec = .1 ms•Controller time–2ms•Average disk access time–12 + 5.6 + 0.1 + 2 ms = 19.7 ms–3 + 5.6 + 0.1 + 2 ms = 10.7 msAugust 1, 2001 Systems Architecture II 8Buses•Shared communication link which uses one or more wires to connect multiple subsystems–versatile–low cost–can be bottleneck–physical limits (length of wire)–conflicting goals (fast bus access vs. high bandwidth)–must support a range of devices•Types of buses–Processor-memory (short, high-speed, custom)–Backplane (high speed, often standardized, e.g. PCI)–I/O (lengthy, not directly connected to memory, multiple types of devices, often standardized, e.g. SCSI)August 1, 2001 Systems Architecture II 9Bus ConfigurationsProcessor MemoryBackplane busa. I/O devicesProcessor MemoryProcessor-memory busb.BusadapterBusadapterI/ObusI/ObusBusadapterI/ObusProcessor MemoryProcessor-memory busc.BusadapterBackplanebusBusadapterI/O busBusadapterI/O busAugust 1, 2001 Systems Architecture II 10Bus Input and Output97018/PattersonFig. 8.07Memory ProcessorControl linesData linesDisksMemory ProcessorControl linesData linesDisksProcessorControl linesData linesDisksa.b.c.MemoryMemory ProcessorControl linesData linesDisksProcessorControl linesData linesDisksa.b.Memory97108/PattersonFig. 8.08Output Operationa) Read requestb) memory accessc) memory transferInput Operationa) Write requestb) memory transferAugust 1, 2001 Systems Architecture II 11Synchronous vs. Asynchronous•Synchronous–use a clock and a synchronous protocol–fast and small–but every device must operate at same rate and–clock skew requires the bus to be short•Asynchronous–don’t use a clock and instead use handshaking–can accommodate a wide variety of devices–can be lengthenedAugust 1, 2001 Systems Architecture II 12Handshaking Protocol•ReadReq–Used to indicate a read request for memory. Address put on the data lines at the same time•DataRdy–Used to indicate that data is now ready on the data lines. Data is placed on data lines at the same time (set by either memory or device depending on whether it is an output or input operation)•Ack–Used to acknowledge the ReadReq of DataRdy signals•ReadReq and DataRdy asserted until the other party has seen the control lines and the data lines have been read. This indication is made by asserting the Ack signal.August 1, 2001 Systems Architecture II 13Handshaking ProtocolDataRdyAckDataReadReq134576422August 1, 2001 Systems Architecture II 14FSM Control for Handshaking Protocol1Record fromdata linesand assertAckReadReqReadReq________ReadReqReadReq3, 4Drop Ack;put memorydata on datalines; assertDataRdyAckAck6Release datalines andDataRdy___________Memory2Release datalines;