System BusesOutlineIntroductionIntroduction (cont’d)Slide 5Slide 6Slide 7Bus Design IssuesBus WidthBus Width (cont’d)Bus TypeBus OperationsSynchronous BusSynchronous Bus (cont’d)Slide 15Slide 16Slide 17Slide 18Asynchronous BusAsynchronous Bus (cont’d)Bus ArbitrationDynamic Bus ArbitrationDynamic Bus Arbitration (cont’d)Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Example BusesISA BusISA Bus (cont’d)Slide 43PC System BusesPCI BusPCI Bus (cont’d)Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55PCI CommandsPCI Commands (cont’d)PCI OperationsPCI Operations (cont’d)Slide 60PCI Bus ArbitrationPCI Bus HierarchiesPCI Bus Hierarchies (cont’d)PCI DelaysAGPAGP (cont’d)Slide 67Slide 68PCI-X BusPCI-X Bus (cont’d)Slide 71PCMCIA BusPCMCIA Bus (cont’d)Slide 74Slide 75Slide 76Slide 77Slide 78Slide 79Slide 80Slide 81Slide 82System BusesChapter 5S. Dandamudi2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 2Outline•Introduction•Bus design issuesBus widthBus typeBus operations•Synchronous busBus operationWait statesBlock transfer•Asynchronous bus•Bus arbitrationDynamic bus arbitrationImplementation»Centralized»Distributed•Example busesISAPCIAGPPCI-XPCMCIA2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 3Introduction•System buses»Internal–PCI–AGP–PCMCIA, …–Focus of this chapter»External–USB–FireWire, …–Discussed in Chapter 192003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 4Introduction (cont’d)•Bus transactionsSequence of actions to complete a well-defined activity»Memory read, memory write, I/O read, burst read–Master initiates the transactionA slave responds•Bus operationsA bus transaction may perform one or more bus operations•Bus cycleEach operation may take several bus cycles»Each is a bus clock cycle2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 5Introduction (cont’d)2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 6Introduction (cont’d)•System bus consists ofAddress busData busControl bus•Buses can beDedicatedMultiplexedSynchronousAsynchronous2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 7Introduction (cont’d)•Control busMemory read and Memory writeI/O read and I/O writeReadyBus request and Bus grantInterrupt and Interrupt acknowledgementDMA request and DMA acknowledgementClockReset2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 8Bus Design Issues•Need to consider several design issuesBus width»Data and address busesBus type»Dedicated or multiplexedBus operations»Read, write, block transfer, interrupt, …Bus arbitration»Centralized or distributedBus timing»Synchronous or asynchronous2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 9Bus Width•Data bus widthA critical parameter in determining system performanceNeed not correspond to the ISA-specific value»Pentium is a 32-bit processor–But has 64-bit data bus»Itanium is a 64-bit processor–But has 128-bit data busThe wider the data bus, the better»Wider buses are expensive2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 10Bus Width (cont’d)•Address bus widthDetermines the system addressing capacityN address lines directly address 2N memory locations»8086: 20 address lines–Could address 1 MB of memory»Pentium: 32 address lines–Could address 4 GB of memory»Itanium: 64 address lines–Could address 264 bytes of memory2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 11Bus Type•Dedicated busesSeparate buses dedicated to carry data and address informationGood for performance»But increases cost•Multiplexed busesData and address information is time multiplexed on a shared busBetter utilization of busesReduces cost2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 12Bus Operations•Basic operationsRead and write•Block transfer operationsRead or write several contiguous memory locations»Example: cache line fill•Read-modify-write operationUseful for critical sections•Interrupt operation•Several other types…2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 13Synchronous Bus•A bus clock signal provides timing information for all actionsChanges occur relative to the falling or rising edge of the clockChoosing appropriate clock is importantEasier to implementMost buses are synchronous•Bus operations can be With no wait states, orWith wait states2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 14Synchronous Bus (cont’d)•Memory read operation with no wait states2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 15Synchronous Bus (cont’d)•Memory write operation with no wait states2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 16Synchronous Bus (cont’d)•Memory read operation with a wait state2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 17Synchronous Bus (cont’d)•Memory write operation with a wait state2003To be used with S.
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