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UCLA COMSCI M151B - chapter5

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System BusesOutlineIntroductionIntroduction (cont’d)Slide 5Slide 6Slide 7Bus Design IssuesBus WidthBus Width (cont’d)Bus TypeBus OperationsSynchronous BusSynchronous Bus (cont’d)Slide 15Slide 16Slide 17Slide 18Asynchronous BusAsynchronous Bus (cont’d)Bus ArbitrationDynamic Bus ArbitrationDynamic Bus Arbitration (cont’d)Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Example BusesISA BusISA Bus (cont’d)Slide 43PC System BusesPCI BusPCI Bus (cont’d)Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55PCI CommandsPCI Commands (cont’d)PCI OperationsPCI Operations (cont’d)Slide 60PCI Bus ArbitrationPCI Bus HierarchiesPCI Bus Hierarchies (cont’d)PCI DelaysAGPAGP (cont’d)Slide 67Slide 68PCI-X BusPCI-X Bus (cont’d)Slide 71PCMCIA BusPCMCIA Bus (cont’d)Slide 74Slide 75Slide 76Slide 77Slide 78Slide 79Slide 80Slide 81Slide 82System BusesChapter 5S. Dandamudi2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 2Outline•Introduction•Bus design issuesBus widthBus typeBus operations•Synchronous busBus operationWait statesBlock transfer•Asynchronous bus•Bus arbitrationDynamic bus arbitrationImplementation»Centralized»Distributed•Example busesISAPCIAGPPCI-XPCMCIA2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 3Introduction•System buses»Internal–PCI–AGP–PCMCIA, …–Focus of this chapter»External–USB–FireWire, …–Discussed in Chapter 192003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 4Introduction (cont’d)•Bus transactionsSequence of actions to complete a well-defined activity»Memory read, memory write, I/O read, burst read–Master initiates the transactionA slave responds•Bus operationsA bus transaction may perform one or more bus operations•Bus cycleEach operation may take several bus cycles»Each is a bus clock cycle2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 5Introduction (cont’d)2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 6Introduction (cont’d)•System bus consists ofAddress busData busControl bus•Buses can beDedicatedMultiplexedSynchronousAsynchronous2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 7Introduction (cont’d)•Control busMemory read and Memory writeI/O read and I/O writeReadyBus request and Bus grantInterrupt and Interrupt acknowledgementDMA request and DMA acknowledgementClockReset2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 8Bus Design Issues•Need to consider several design issuesBus width»Data and address busesBus type»Dedicated or multiplexedBus operations»Read, write, block transfer, interrupt, …Bus arbitration»Centralized or distributedBus timing»Synchronous or asynchronous2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 9Bus Width•Data bus widthA critical parameter in determining system performanceNeed not correspond to the ISA-specific value»Pentium is a 32-bit processor–But has 64-bit data bus»Itanium is a 64-bit processor–But has 128-bit data busThe wider the data bus, the better»Wider buses are expensive2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 10Bus Width (cont’d)•Address bus widthDetermines the system addressing capacityN address lines directly address 2N memory locations»8086: 20 address lines–Could address 1 MB of memory»Pentium: 32 address lines–Could address 4 GB of memory»Itanium: 64 address lines–Could address 264 bytes of memory2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 11Bus Type•Dedicated busesSeparate buses dedicated to carry data and address informationGood for performance»But increases cost•Multiplexed busesData and address information is time multiplexed on a shared busBetter utilization of busesReduces cost2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 12Bus Operations•Basic operationsRead and write•Block transfer operationsRead or write several contiguous memory locations»Example: cache line fill•Read-modify-write operationUseful for critical sections•Interrupt operation•Several other types…2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 13Synchronous Bus•A bus clock signal provides timing information for all actionsChanges occur relative to the falling or rising edge of the clockChoosing appropriate clock is importantEasier to implementMost buses are synchronous•Bus operations can be With no wait states, orWith wait states2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 14Synchronous Bus (cont’d)•Memory read operation with no wait states2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 15Synchronous Bus (cont’d)•Memory write operation with no wait states2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 16Synchronous Bus (cont’d)•Memory read operation with a wait state2003To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. S. Dandamudi Chapter 5: Page 17Synchronous Bus (cont’d)•Memory write operation with a wait state2003To be used with S.


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