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UCLA COMSCI M151B - hw2

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CS M151Bhw2Shengqian Liu9043472481.2.If 0 is carried in, and 1 is carried out, the only way is that both MSBs of A and B is 1. That way, the sum is 0, and the carry out is 1. This is the case when we add two negative numbers, but the sum is nonnegative, and this is row 2 and 4 in figure 3.2.If 1 is carried in, and 0 is carried out, the only way is that both MSBs of A and B is 0. In that case, 1 is the sum and 0 is carried out. This is the case when we add two non-negative numbers and get a negative result, and this is row 1 and 3 in figure 3.2.3.ALU Function0000 AND0001 OR0010 add0110 subtract0111 slt1100 NORIf bit-1 is stuck-at-1, then for AND, the ALU control lines will be 0010 which is actually add, so every time the users want to perform AND,they will actually get the addition as their results.for OR, the ALU control line will be 0011. 11 as the Op code means that it will perform slt operation. However, 0 as the Bnegate means that the ALU will not perform A - B but A + B during the calculation. Therefore the users will get wrong slt results when they want to perform OR operation.for add, the users will not observe a difference.for subtract, the users will not observe a difference.for slt, the users will not observe a difference.for NOR, the ALU control lines will be 1110 instead if 1100. As a result, the ALU will negate both A and B and perform add rather than do the NOR operation.4.If MemRead becomes 0 when RegDst control is 0, then lw instruction won’t work properly. To test for this fault, we can execute a lw with a non-zero address that stores a word. If the MemRead becomes 0, the rt register won’t have the proper word loaded.5.We cannot make a guaranteed working test for this fault because for all instructions except jump instructions, the jump signal is 0. Therefore even if Jump becomes 0 if RegDst is 0, the processor still operates correctly. For jump instructions, the RegDst is don’t care; therefore even if this fault exists, we can’t write a robust test because we don’t know what the RegDst is. Maybe we can write many jump instructions and maybe some of their RegDst would be 0 and in those cases, the jump won’t work as the Jump signal is set to 0.6.RegDst 0 - Mux A is set to 0 meaning the register destination number for the Write register comes from the rt field.Jump 0- Mux B is et to 0 meaning the PC will be set to result from Mux C.Branch 0- AND gate D will give result of 0 as Branch signal is 0. As a result, Mux C will be set to 0 meaning PC will be set to PC + 4MemRead 1- Data memory contents designated by the address input are put on the Read data output.MemtoReg 0- Mux E is set to 0 meaning the value fed to the register Write data input comes from the ALU.ALUOp MSB 0ALUOp LSB 1- ALU Opcode is 01 which means it’s a beq instruction and ALU control input will be set to 0110 (sub)MemWrite 1- Data memory contents designated by the address input are replaced by the value on the Write data input.ALUSrc 0- Mux F is set to 0 meaning the second ALU operand comes from the second register file output (Read data2).RegWrite 1- The register on the Write register input is written with the value on the Write data


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