CS M151Bhw3Shengqian Liu9043472481.The circuit will malfunction if it wants RegWrite to be 0 and ALUSrcB to be 1x or it wants RegWrite to be 1 and ALUSrcB to be 0x at the same circle.Instruction fetch and decode won’t be affected because RegWrite is don’t care. For LW instructions, since both MSB of ALUSrcB and RegWrite need to be 1, they will behave correctly.For SW insructions, since RegWrite is don’t care, they will behave normally.For R-type instructions, in the Execution state (state 6), its sets ALUSrcB to 00 and in the completion state, its sets RegWrite to 1. However, because they are two separate circles, in other words, it doesn’t matter if ALUSrcB is set to 10 in the completion circle because the ALU has already done its job correctly in the execution circle, R-type instructions will behave correctly.For BEQ and Jump instructions, RegWrite is don’t care so they have no problem.Therefore a user won’t feel a difference for this hardware fault.2.A) I made four modifications to the datapath.1. Extended ALUSrcA signal to 2 bits as well as the Mux that uses this signal. I feed 1 to the extra input to the mux so that the ALU can calculate 1 + rt.2. Introduced an extra Adder that will add 4 to the sign-extended immediate to get the immediate for the second address.3. Extended ALUSrcB signal to 3 bits as well as the Mux that uses this signal. I feed the result of the extra adder to the extra input to this mux so that the ALU can calculate the second address ( (immediate + 4)($rs))4. Added an extra signal ‘srp’ and an extra Mux so that the Registers File can select rt + 1 asRead register 2B) see third pageC) Yes, I added an extra signal ‘srp’ and an extra Mux so that the Registers File can select rt + 1 as Read register 2.D) IR ← M[PC]; PC ← PC + 4; Next;A ← R[IR25..21]; B ← R[IR20..16]; Next;switch(IR31..26) {case 0: /* R-format */switch(IR5..0) {case 32: /* add */ALUout ← A + B; Break;case 34: /* sub */...}Next ;R[IR15..11] ← ALUout ; Break ;case 35: /* lw */ALUout ← A + SignExt (IR15..0); Next;MDR ← M[ALUout ]; Next ;R[IR20..16] ← MDR; Break;case 43: /* sw */...case 23: /* srp */ALUout <- A + SignExt(IR 15..0);Next;M[ALUout] <- B;Next;ALUout <- 1 + R[IR20..16]; B <- ALUout; Next;ALUout <- A + SignExt(IR 15..0) + 4; Next;M[ALUout] <- B; Break;}Next ;E) see fourth pageF) ROMcont : 16 x 19 = 304 bitsROMstate: 1024 x 4 = 4096 bitstotal: 4400 bitsTables: see fifth and sixth page.X X X X X X X X X 0 0 1 0 1 X X 1 0X X X X X X 1 X X X X X X X 1 0 0 0X X X X X X X X X 1 0 0 0 1 X X 1 1X 1 X X X X X 0 1 0 1 0 0 1 X X 0 03.word2word4word6word84. For Figure D.4.1, add one more signal output RegSrc No change needed for Figure D4.25.Jump instructions are the fastest instructions and the only delay they experience is in the Memorycomponent, which is 5ns.If all the instructions are jump instructions, then we have the maximum possible clock frequency, which is 1 / 5ns = 200
View Full Document
Unlocking...