EE 2008 Fall 2008EE 231Exam 3November 19, 2008Name:Show all work. Partial credit will be given. No credit will be given if an answer appears with no supportingwork.1. Circle the correct answer to questions (a) through (i); give a numerical answer for (j) and (k):(a) A movement of data from right (least significant bit) to left (most significant bit) is what type ofshift:A. Right B. Left C. Parallel D. Finite state machine(b) A serial shift register with non-complemented feedback from the output of the last flip-flop tothe input of the first is called a:A. Binary Counter B. Gray Code Counter C. Johnson Counter D. Ring Counter(c) A finite state machine in which the output depends on the present state and the present inputs iscalled a:A. Mealy machineB. Mannie machine C. Moore machine D. Vending machine(d) A finite state machine in which the output depends only on the present state is called a:A. Mealy machine B. Mannie machine C. Moore machine D. Vending machineQVCCVCC(e) The circuit shown above is used for what purpose?A. Counter B. Pulser C. Shift register D. Switch debounce(f) The multiplexer is an example of what type of Boolean circuit?A. Sequential B. Combinational C. Moore machine D. Analog(g) Which sequential device has an output that is only dependent on the level of the inputs?A. Latch B. Multiplexer C. Flip-Flop D. Clock Tree1EE 2008 Fall 2008module ex3 (input clock, clear, load, x, output reg y)always @(posedge clock, negedge clear)if (clear == 1’b0) y <= 0;else if (load == 1’b0) y <= x;else y <= y;endmodule(h) For the Verilog code above, what type on input is clear?A. Latched B. Synchronous C. Asynchronous D. Tri-statemodule ex3 (input clock, clear, x, output reg y)always @(posedge clock, negedge clear)if (clear == 1’b0) y <= 0;else if (load == 1’b0) y <= x;else y <= y;endmodule(i) For the Verilog code above, what type on input is load?A. Latched B. Synchronous C. Asynchronous D. Tri-state(j) A finite state machine has eleven states. (The number of states cannot be reduced.) What is theminimum number of flip-flops needed in the state register?4. 23= 8 and 24= 16, so 3 flip-flops will only allow for 8 states, and 4 flip-flops will allow forup to 16 states.(k) A finite state machine has eleven states. (The number of states cannot be reduced.) What is thenumber of flip-flops needed in the state register if the design is done using one-hot assignment?11. One-hot means one flip-flop per state, so 11 states require 11 flip-flops..2EE 2008 Fall 20082. A traffic signal controller has two inputs (plus a clock) and three outputs. The inputs are E (for east-west traffic) and N (for north-south traffic). The outputs are R (red light), Y (yellow light) and G(green light). The system is to behave as follows: G will be high for two clock cycles. If E is high onthe second clock cycle, G will stay high for one more clock cycle. After this, Y will go high for oneclock cycle, then R will go high for two clock cycles. If N is high on the second R-high clock cycle,R will stay high for one more clock cycle. After this, R and Y will go high at the same time, then thesystem will go back to the start of the sequence.Draw a state diagram for this system.Inputs are of the form EN. Moore outputs (in the state circles) are of the form RYG. The light will begreen for two or three states, so I made states G1, G2 and G3. It will be red for two or three states, soI made state R1, R2 and R3. It will be yellow for one state (Y) and red-yellow for one state (RY). Ifwill go from G1 to G2. In G2, it will go to G3 if E is 1, and will go to Y is E is 0. From G3, it willalways go to Y. From Y, it will go to R1, the R2. In R2, it will go to R3 if N is 1, and to RY is N is 0.From R3, it will always go to RY. From RY it will always go to G1.xxG1001 001 001G2 G3R1R2R3RY010100100100110Yxx 1x0x xxxxxxx0x1xx3EE 2008 Fall 20083. Consider the circuit below.xDQQDQQzClockD2Q1Q2D1(a) Is this a Mealy or a Moore machine? Why?This is a Moore machine. The ouput z depends only on the state registers Q1and Q2, and noton the input x.(b) Write Boolean equations for the flip-flop inputs D1and D2and the system output z.D1= x · (Q1+ Q2)D2= x · (Q01+ Q02).z = Q1Q02(c) Tabulate the state transition table for the circuit.Present Input Next OutputStateStateQ2Q1x Q2Q1z0 0 0 0 0 00 0 1 1 0 00 1 0 0 0 10 1 1 1 1 11 0 0 0 0 01 0 1 1 1 01 1 0 0 0 01 1 1 0 1 04EE 2008 Fall 2008(d) Draw a state diagram for the system.Moore outputs are inside the state circles. Inputs are on the transition arrows, showing whichbranch the system will take for the given inputs.1010000110 1100000 1115EE 2008 Fall 20084. The Verilog code program below describes a universal counter:module ucntr( input clk, clear, ena, dir, load,input [3:0] D,output reg [3:0] Q);always @(posedge clk)if (clear) Q <= 4’h0;else if (load) Q <= D;else if (ena & dir) Q <= Q + 4’h1;else if (ena & ˜dir) Q <= Q - 4’h1;else Q <= Q;endmoduleShow what will be on the outputs Q and z for the following inputs:Date: December 12, 2008 db/counter.sim.cvwf*Project: counterPage 1 of 1Revision: counterclkclearloadenadirDQz3 5 2 7 14 3 5 6 7 6 0 1151.349 ns +99.612 ns +199.225 ns +297.328 ns +399.958 ns +498.061 ns +597.673 ns +700.304 ns +799.916 ns +901.038 ns110.0 ns 750.0 ns 1.15