NMT EE 231 - EE 231 Lab 1 (3 pages)

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EE 231 Lab 1



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EE 231 Lab 1

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Pages:
3
School:
New Mexico Institute of Mining and Technology
Course:
Ee 231 - Digital Electronics

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EE 231 Fall 2011 EE 231 Lab 1 HCMOS Logic Family In this lab you will get a hands on experience designing simple logic circuits using standard integrated circuits ICs You will learn about timing and its effect on the circuit output 1 Prelab 1 2 3 4 Write the truth table for an inverter gate Write the truth table for an xor gate Write the truth table for a and gate Write the truth table for the circuit shown in Figure 1 Figure 1 A simple circuit 2 Lab 2 1 Basic Behavior of HCMOS Logic Family 1 Use the datasheet to connect a 7404 IC 2 Verify the operation of an inverter by connecting the input to Vcc and GND 3 Use a variable 10k pot to vary the input to the inverter as shown in Figure 2 When does the input change Figure 2 Changing the input to the inverter 4 Build the circuit shown in Figure 1 using 10 inverters in series Set the output of the function generator that you built in Lab 0 to 15kHz and connect it to the input of your circuit Can you observe the output of your circuit by using a voltmeter or 1 EE 231 Fall 2011 a logic probe 5 Connect the output of your circuit to the logic analyzer and record your observations Use the information provided in section 3 to run the logic analyzer 6 Does the output match what you expected Why or why not 7 What is the propagation delay of an inverter gate 3 Half Adder 1 Write the truth table for the circuit shown in Figure 3 2 Connect ICs from the 7400 IC to implement the circuit shown above 3 Verify that operation of the circuit by connecting the inputs to different combinations of Vcc and GND 4 In terms of binary arithmetic what do the S and C outputs represent Figure 3 Half Adder Circuit 4 Supplementary Material 4 1 Logic Analyzer Start the logic analyzer by double clicking on the LA Viewer icon on the Windows desktop Do the following 1 From the Clock menu in the upper right corner of the LA Viewer window set the internal clock for a 5 MHz sampling rate 2 Right click in the left most column of the viewing area and select



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