EE 231 Lab Fall 2007______________________________________________________________________________________EE 231L Lab 2Design and Implementation of Combinational CircuitsPart 1. The Decoder Circuit1. Build the decoder circuit you designed in the pre-lab using HCMOS logic chips.2. Test your circuit with your logic probe, and confirm that it functions for all possible input combinations. Have your lab instructor or TA verify the circuit works.Part 2. Decoder Circuit in Altera1. Program the decoder circuit in Altera using a Graphics Design File.2. Program the decoder circuit in Altera using a Text Design File.3. Simulate the circuit with Altera’s waveform editor.4. Test your circuit with your logic probe, and confirm that it functions for all possible input combinations. Have your lab instructor or TA verify the circuit works.Part 3. Arithmetic Logic UnitThe heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of thecomputer which performs arithmetic operations on numbers, e.g. addition, subtraction, etc. Hereyou will use the Verilog language to implement an ALU having 11 functions.ALU OperationsYour ALU will perform 11 functions on two 8-bit inputs. Later on this ALU will be one component of the computer you build in the final lab. At that time the ALU inputs will be from the DATA bus, ACCA (Accumulator A) and X (X register). To help make the transition to the computer, you should call the inputs [7:0] DATA, [7:0] ACCA, and [7:0] X. These inputs could represent either unsigned numbers, two’s complement numbers, or non-numeric bit patterns. The ALU will generate an 8-bit result (result), a one bit carry (C) and a one-bit zero bit (Z). To select which of the 11 functions to implement you will use ALU_CTL as selection lines. You will decide which combination of bits in the selection lines ALU_CTL correspond to for each instruction. The 11 functions are described in Table 1.1EE 231 Lab Fall 2007______________________________________________________________________________________Figure 1. ALU block diagramIt is up to you do determine how many control lines are necessary to select the ten different functions.ALUZC[7:0] Result[7:0] X[7:0] Data[7:0] ACCA[?:0 ] ALU_CTL2EE 231 Lab Fall 2007______________________________________________________________________________________Table 1. ALU FunctionsALU_CTL Mnemonic DescriptionLoad(load DATA into result)DATA=>result: Output=DATA inputC is a don’t care1→Z if result==0, 0→Z otherwiseADDA(add DATA to ACC.)ACCA+DATA=>result: Add DATA and ACCAC is carry from addition1→Z if result==0, 0→Z otherwiseSUBA(substract data from ACC.)ACCA-DATA=>result: Subtract DATA from ACCAC is borrow from subtraction1→Z if result==0, 0→Z otherwiseANDA(logical AND of DATA with ACC.)ACCA&DATA=>result: Logical AND DATA and ACCAC is a don’t care1→Z if result==0, 0→Z otherwiseORAA(logical OR of DATA with ACC.)ACCA#DATA=>result: Logical OR DATA and ACCAC is a don’t care1→Z if result==0, 0→Z otherwiseCOMA(complement of ACC.)_____ACCA =>result: One’s complement of ACCA1=> C1→Z if result==0, 0→Z otherwiseINCA(increment ACC.)ACCA+1=>result: Add one to the values in ACCAC is a don’t care1→Z if result==0, 0→Z otherwiseLSRA(logical shift right of ACC.)Shift all bits of ACCA one place to the right0=>result[7], ACCA[7..1] →result[6..0], ACCA[0]=>C1→Z if result==0, 0→Z otherwiseLSLA(logical shift left of ACC.)Shift all bits of ACCA one place to the left0=>result[0], ACCA[6..0] →result[7..1], ACCA[7]=>C1→Z if result==0, 0→Z otherwiseASRA(arithmetic shift right ACC.)Shift all bits of ACCA one place to the rightACCA[0]=>result[7], ACCA[7..1] →result[6..0], ACCA[0]=>C1→Z if result==0, 0→Z otherwiseCPX(compare X to DATA)X- DATA=>result: Subtract DATA from XC is borrow from subtraction1→Z if result==0, 0→Z otherwise1. Design your ALU using Altera. Use a Text Design File. Be certain to deal with any unused bit combinations of the ALU_CTL lines in your Verilog program. If for any reason ALU_CTL should have an undefined bit pattern on its lines during operation you should know what output will be produced.2. Simulate the ALU using the Altera simulator. Test multiple combinations of DATA, ACCA and X. Choose test values that will test all possibilities for the carry and zero bits.3. Program your ALU code into your FPGA. Verify that it works, using the test data from your simulation.3EE 231 Lab Fall 2007______________________________________________________________________________________4. Make your code into an Verilog function called ALU. Verify that you can call this function from another Altera