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EE 231L Fall 2005EE 231L Lab 5Putting it All Together: Building the ComputerIn this lab you will put the parts of the computer together to build a functional computer. Thisis just a matter of including the blocks in a tdf file, and defining the inputs to and the outputs fromthe blocks in this file. You will also define the other combinational circuits used by the computer,such as a few multiplexers and a decoder.You should do the following:1. Create a file which defines useful constants. For my computer, I defined three sets of constants:the ALU control lines, the memory select control lines, and the computer instructions. Hereare a few lines from my file constants.inc:%*-------------------------------------------------------------------------constants.inc - file to hold all the global constants*-------------------------------------------------------------------------*%%* -- ALU constants -- *%CONSTANT ALU_LOAD = B"0001";% Memory Mux constants %CONSTANT PC_SEL = B"00";% Instruction constants %CONSTANT LDAA = H"01";2. Make a file which includes the Default Include Files of all your blocks. Here are a fewlines from my computer.inc file, which contain the prototypes for the ALU and the 8-bitsynchronous load register (which is used for, among other blocks, ACCA):%*-------------------------------------------------------------------------computer.inc - file which contains prototypes of blocks usedin computer design*-------------------------------------------------------------------------*%FUNCTION alu(din[7..0], acca[7..0], ctrl[3..0])RETURNS(dout[7..0], cout);FUNCTION load_reg(din[7..0], reg_l, clock)RETURNS(dout[7..0]);1EE 231L Fall 20053. Create the file for the final computer design. Here are some lines from my file computer.tdf— I included the parts which define the inputs to the ALU and ACCA:INCLUDE "constants.inc";INCLUDE "computer.inc";SUBDESIGN computer(prog_addr[7..0] : INPUT;prog_data[7..0] : INPUT;port_in[7..0] : INPUT;reset : INPUT;clock : INPUT;prog_r : INPUT;prog_w : INPUT;addr_out[7..0] : OUTPUT;port_out[7..0] : OUTPUT;mem_r : OUTPUT;mem_w : OUTPUT;mem_cs : OUTPUT;mem_data[7..0] : BIDIR;)VARIABLEmy_alu : alu;acca : load_reg;BEGIN% Define the inputs to the ALU %my_alu.din[] = mem_data[]; % din comes from memory bus %my_alu.acca[] = acca.dout[]; % acca comes from the outputs of ACCA %my_alu.ctrl[] = ctrl.alu_ctl[]; % ctl comes from the control machine %% Define the inputs to the ACCA %acca.din[7..0] = my_alu.dout[]; % din comes from ALU %acca.reg_l = ctrl.acca_l; % load enable comes from control machine %acca.clock = clock; % clock is the global clock %You should write this file in pieces – for example, start with the control unit, and make surethat part compiles. (The control unit uses inputs from the instruction register and the carry,which have not yet been defined. Just assign those inputs to a constant value to start, andput in the correct inputs when the appropriate parts are added. For example, you might startwithctrl.inst[] = H"00";2EE 231L Fall 2005After you add the instruction register, you should change this to:ctrl.inst[] = inst_reg.dout[];4. Simulate the function of the c omputer. In your simulation, include the inputs to and theoutputs from the computer, and the values of the internal registers. Attached is a copy of mysimulation. You need to supply the values for the data from memory. I did my simulation byhaving a clock with an input frequency of 1 MHz. I started with the reset input low, andmade sure the control lines from the control state machine were in the proper states. I thenbrought reset high, and reran the simulation. In order to get data from the memory, bothmem_cs and mem_r need to be low. When either of these lines were high, I made the input onmem_data[] to be ZZ (high-impedance). When mem_cs and mem_r were both low, I put thevalues appropriate for the address on the mem_data[] lines. I assumed the following programwas in the memory:LDAA #0x23ADAA 0xF0STAA 0xF1This is what I assumed would be in the necessary memory locations:Address Data0x00 0x020x01 0x2A0x02 0x040x03 0xF00x04 0x030x05 0xF10xF0 0xEB0xF10x00At the start of the simulation, when mem_cs and mem_r were both low, and addr_out[] wasat 0x00, I put an 0x02 on the mem_data[] input lines. I then reran the simulation. In thenext cycle, when the addr_out[] was at 0x01, I put an 0x2A on the mem_data[] input lines.The instruction LDAA #0x23 is a two-cycle instruction. At the end to the second cycle, Iverified that 0x23 was loaded into ACCA.I kept going to simulate the ADDA 0xF0 instruction, and verified the ACCA contained a 0x15(0x2A + 0xEB), and that the carry was set. I then simulated the STAA 0xF1 instruction, toverify that the value in ACCA was put on the mem_data[] output lines, and that mem_cs andmem_w were both low, so that the value in ACCA would be written into memory address 0xF1.I replaced the ADDA 0xF0 instruction with SUBA 0xF0 to verify that the SUBA instructionworked correctly. I continued until I verified that all the instructions worked properly.5. I then tested the input and output ports. I simulated the instructions LDAA 0xFF to verify thatthe system would load data from the input port, and simulated the STAA 0xFF instruction toverify that the system would write data to the output port.3EE 231L Fall 2005After the simulation works, it is time to program the computer into an Altera chip. The totalproject is too large to fit into your EPM7064 chip. We will have some printed circuit boards whichhave a larger Altera chip (an EPF8636) and a memory chip. You will use these to implement yourcomputer. We will only have a few of these systems, so you will probably have to work in groupsfor your implementation. I will update this lab with more details next week.4MAX+plus II 10.1 File: C:\DOCUMENTS AND SETTINGS\WILLIAM RISON\MY DOCUMENTS\ACADEMIC\EE231\FALL 05\COMPUTER RISON\COMPUTER.SCF Date: 11/10/2005 16:53:24 Page: 1[I] reset[I] clock[I] prog_w[I] prog_r[I] prog_addr[7..0][I] port_in[7..0][O]addr_out[7..0][O]port_out[7..0][I] mem_data[7..0][O]mem_data[7..0][B] c_reg:pc|dout[7..0][B] _reg:inst|dout[7..0][B] reg:acca|dout[7..0][B] c.Q[O]mem_w[O]mem_r[O]mem_cs[B] |control:ctrl|ss00AA00 01 02 03 F0 04 05 F1 06 07 F2 08 0900ZZ 02 2A 04 F0 EB 03 F1 ZZ 05 F2 37 0A ZZZZ 02 2A 04 F0 EB 03 F1 15 05 F2 37 0A ZZ00 01 02 03 04 05 06 07 08 0900 02 04 03 05 0A00 2A 15 DE DFRST C1 C2 C1 C2 C3 C1 C2 C3 C1 C2 C3 C1 C2 C11.0us 2.0us 3.0us 4.0us 5.0us 6.0us 7.0us 8.0us 9.0us 10.0us 11.0us


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