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NMT EE 231 - EE 231L Lab 2

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EE 231L Fall 2006EE 231L Lab 2Design and Implementation of Combinational CircuitsPart 1. The Decoder Circuit1. Build the decoder circuit you designed in the pre-lab using HCMOS logic chips.2. Test your circuit with your logic probe, and confirm that it functions for all possible inputcombinations. Have your lab instructor or TA verify the circuit works.Part 2. Decoder Circuit in Altera1. Program the decoder circuit in Altera using a Graphics Design File.2. Program the decoder circuit in Altera using a Text Design File.3. Simulate the circuit with Altera’s waveform editor.4. Test your circuit with your logic probe, and confirm that it functions for all possible inputcombinations. Have your lab instructor or TA verify the circuit works.Part 3. Arithmetic Logic UnitThe heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of thecomputer which performs arithmetic operations on numbers, e.g. addition, subtraction, etc. Hereyou will use the Altera language to implement an ALU having 11 functions.ALU OperationsYour ALU will perform 11 functions on two 8-bit inputs. Later on this ALU will be one componentof the computer you build in the final lab. At that time the ALU inputs will be from the DATAbus, ACCA (Accumulator A) and X (X register). To help make the transition to the computer, youshould c all the inputs DATA[7..0], ACCA[7..0], and X[7..0]. These inputs could represent eitherunsigned numbers, two’s complement numbers, or non-numeric bit patterns. The ALU will generatean 8-bit result (result), a one bit carry (C) and a one-bit zero bit (Z). To select which of the 11functions to implement you will use ALU_CTL as selection lines. You will decide which combinationof bits in the s ele ction lines ALU_CTL correspond to for each instruction. The 11 functions aredescribed in Table 1.1EE 231L Fall 2006ACCA[7..0]CALU_CTL[?..0]ALUDATA[7..0] X[7..0]Zresult[7..0]Figure 1. ALU block diagram.It is up to you to determine how many control lines are necessary to select the ten diffe rent functions.Table 1. ALU Functions.2EE 231L Fall 2006ALU_CTL Mnemonic DescriptionLoad DATA => result: Output = DATA input(load DATA into result) C is a don’t care1 -> Z if result === 0, 0 -> Z otherwiseADDA ACCA+DATA => result: Add DATA and ACCA(add)C is carry from addition1 -> Z if result === 0, 0 -> Z otherwiseSUBA ACCA-DATA => result: Subtract DATA from ACCA(subtract) C is borrow from subtraction1 -> Z if result === 0, 0 -> Z otherwiseANDA ACCA & DATA => result: Logical AND(logical AND) C is a don’t care1 -> Z if result === 0, 0 -> Z otherwiseORAA ACCA # DATA => result: Logical OR(logical OR) C is a don’t care1 -> Z if result === 0, 0 -> Z otherwiseCOMA ACCA => result: One’s complement of ACCA(complement) 1 => C1 -> Z if result === 0, 0 -> Z otherwiseINCA ACCA + 1 => result: Add one to the value in ACCA(increment) C is a don’t care1 -> Z if result === 0, 0 -> Z otherwiseLSRA Shift all bits of ACCA one place to the right(logical shift right) 0 => result[7], ACCA[7..1] -> result[6..0], ACCA[0] => C1 -> Z if result === 0, 0 -> Z otherwiseLSLA Shift all bits of ACCA one place to the left(logical shift left) 0 => result[0], ACCA[6..0] -> result[7..1],ACCA[7] => C1 -> Z if result === 0, 0 -> Z otherwiseASRA Shift all bits of ACCA one place to the right(arithmetic shift right) ACCA[0] => result[7], ACCA[7..1] -> result[6..0],ACCA[0] => C1 -> Z if result === 0, 0 -> Z otherwiseCPX X-DATA => result: Subtract DATA from X(compare X to DATA) C is borrow from subtraction1 -> Z if result === 0, 0 -> Z otherwise1. Design your ALU using Altera. Use a Text Design File. Be certain to deal with any unusedbit combinations of the ALU_CTL lines in your Altera program. If for any reason ALU_CTLshould have an undefined bit pattern on its lines during operation you should know whatoutput will be produced.2. Simulate the ALU using the Altera simulator. Test multiple combinations of DATA, ACCA andX. Choose test values that will test all possibilities for the carry and zero bits.3. Program your ALU code into you EPF6016. Verify that it works, using the test data fromyour simulation.3EE 231L Fall 20064. Make your code into an Altera function called ALU. Verify that you can call this functionfrom another Altera TDF


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