NMT EE 231 - Using Verilog to Design State Machines

Unformatted text preview:

EE 231 Lab Fall 2007______________________________________________________________________________________EE 231LUsing Verilog to Design State MachinesFinite state machine is another name for sequential circuits. A two-bit up-down counter can be described as a state machine with one input and two outputs:The state table for the sequential circuit isPresenty Next State Y w = 0 w = 1OutputzA D B 00B A C 01C B D 10D C A 11A state-assigned table for the circuit looks like thisPresenty Next State Y w = 0 w = 1Outputz00 11 01 0001 00 10 0110 01 11 1011 10 00 11There are a few ways to design state machines using Verilog. Here is one design for the two-bit up-down counter:A/z=00C/z=10D/z=11B/z=01 w = 1 w = 1 w = 0 w = 0 w = 0 w = 0 w = 1 w = 11EE 231 Lab Fall 2007______________________________________________________________________________________The two-bit up-down counter is a Moore machine — i.e., the outputs of the machine depend only on the current state, and not on the current input. You can design a Moore machine by specifying a bit pattern associated with each state. The y[2:1] outputs are directly associated with bits of the state machine. This means that the y[2:1] (z) outputs will be the outputs of flip-flops, and will not change value until the machine changes states.You can use Verilog to design state machines with asynchronous outputs, also called Mealy machines. Here is an example from your textbook:The state table for this sequential circuits isPresent Next State Output zAB Reset w = 1 / z = 0 w = 0/z = 0 w = 1 / z = 1 w = 0/z = 02EE 231 Lab Fall 2007______________________________________________________________________________________State w = 0 w = 1 w = 0 w = 1A A B 0 0B A B 0 1And the state-assigned table is as followsPresentStateNext Statew = 0 w = 1Output zw = 0 w = 1Y Y Y z zA A B 0 0B A B 0 1Here is a Verilog file to implement the design. This example shows how to reset a state machine. When reset goes high, the machine will be reset to the first state in the state machine list; in this case, that will be state A. The reset is done using the asynchronous CLRN (active-low clear)/RESETN (active-low reset) and PRN (active-low preset) inputs to D flip-flops, so the reset is done as soon as reset goes high; it is not necessary to wait for a clock edge.When in state B, the output will be 0 when the input is 0, and the output will be 1 when the input is 1. The output will change multiple times while in state B if the input changes multiple times. For a Moore machine, the output changes only when the machine switches from one state to another.3EE 231 Lab Fall


View Full Document

NMT EE 231 - Using Verilog to Design State Machines

Download Using Verilog to Design State Machines
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Using Verilog to Design State Machines and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Using Verilog to Design State Machines 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?