EE 231 Lab Fall 2007______________________________________________________________________________________EE 231L Lab 4Design and Implementation of State MachinesDesign of a Computer Control UnitIn this lab you will design a control system for a computer. You will design it as a state machine. Be sure to read the handout Using Verilog to Design State Machines. There are also a few other blocks you will need to implement your computer – two multiplexers, a decoder, and a tri-state buffer. In Part 1 of this lab, you will design these other blocks. In Part 2, you will design the computer control unit.Part 1. Other Combinational Circuits.1. Multiplexer.In the diagram of the final computer there is an element labeled MUX. This is a multiplexer. The MEM_SEL lines are the selection lines of the multiplexer. Depending on the state of the MEM_SEL lines, the MUX (multiplexer) will choose to output one of four possible signals: the value in either PROG_ADDR, PC, MAR or X.Write a Verilog program to implement the MUX. (Remember, PROG_ADDR, PC, and MAR are each 8 bits wide).2. Decoder.Directly to the right of the MUX is another computer element. This is the Decoder (DCD). The DCD determines if the memory address output by the MUX is equal to 0xFF.• If the address equals 0xFF then the ADDR_FF line should be brought low. This will allow either the external input or output to be enabled depending on the state of the M_W (memory write) and M_R (memory read) lines.• If the output of the mux is not equal to 0xFF, then the ADDR_NOTFF line should be brought low. When the ADDR_NOTFF line is low, the memory is selected and can be read from or written to (depending on the state of M_W and M_R). Write a Verilog Program to implement the decoder.3. Tri-State Buffer.You will need two tri-state buffers in the final computer. Verilog has an active-hi tri-state buffer (TRI). Here is a program which implements an 8-bit active-low tri-state buffer:1EE 231 Lab Fall 2007______________________________________________________________________________________Part 2. Design of Computer Control Unit.The data-processing functions of the computer are divided into simple units called instructions. A computer program is just a collection of computer instructions. The instruction set of a computer are the basic operations that the computer can perform. The instruction set of our computer is shown in Figure 1.In this lab you will design the computer control unit. The control unit is a finite state machine. Its inputs are the instruction register and the carry, as well as a clock pulse and RESET. The control unit’s outputs are the control signals that direct the operation of the rest of the computer. The control unit can be in one of four states: RESET, C1, C2, C3:RESET is the Reset state. The computer gets into this state when the Reset input is low, and stays in this state until the Reset input goes high.C1 is the Fetch Cycle. The computer program is stored in memory. During the fetch cycle the next instruction is fetched from memory and loaded into the instruction register (INST).C2 is the first bf Execution Cycle. Once an instruction has been loaded into the INST, the control unit determines the required course of action to take based on the value of INST and the current state of the control unit.C3 is the second Execution Cycle. Some instructions only require one execution cycle (C2) while others require two (C2 and C3).The output of the control unit depends on both the present state and the input. (What type of state machine is this?)2EE 231 Lab Fall 2007______________________________________________________________________________________ Mnemonic Operation0 LDAA addr Loads ACCA with the value in memory at address addr load ACCA from memory C stays the same, Z changes1 LDAA #num Loads ACCA with num, the value in memory at the address load ACCA with an immediately following the LDAA #num command immediate C stays the same, Z changes2 LDAA 0,X Loads ACCA with the value in memory at the address load ACCA indexed in the X register. C stays the same, Z changes.3 STAA addr Stores the value in ACCA at the memory address addr store ACCA in memory C stays the same, Z changes4 ADDA addr Adds the value in memory location addr to the value in ACCA add ACCA and value at saves the result in ACCA in memory Z and C change5 SUBA addr Subtracts the value in memory location addr from the value in subtract value in memory ACCA and saves the result in ACCA from ACCA Z and C change6 ANDA addr Perform a logical AND of the value in memory location addr with logical AND of ACCA the value in ACCA. Save result in ACCA and value in memory C stays the same, Z changes.7 ORAA addr Perform a logical OR of the value in memroy location addr with logical OR of ACCA the value in ACCA. Save result in ACCA and value in memory C stays the same, Z changes.8 CMPA addr Compare ACCA to value in addr. This is done by subtracting compares ACCA to the value in addr from ACCA. The C and Z bits the value in addr are changed. ACCA does not change9 LDX #num Loads X with num, the value in memory at the address load X with an immediately following the LDX #num command immediate C stays the same, Z changes.A INX Increment value in X increment X C stays the same, Z changes.B CPX #num Compare X to num, the value in memory at the address compares X to