ECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutTopicsTopics––Low Power TechniquesLow Power TechniquesBased on Penn State CSE477 Lecture Notes ©2002 M.J. Irwin andadapted from Digital Integrated Circuits ©2002 J. RabaeyECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutReview: Energy & Power EquationsReview: Energy & Power EquationsE = E = CCLL V VDDDD2 2 PP00→→11 + + ttscsc V VDDDD I Ipeak peak PP00→→1 1 + + VVDDDD I IleakageleakageP = P = CCLL V VDDDD22 f f00→→1 1 + + ttscscVVDDDD I Ipeakpeak f f00→→1 1 ++ VVDDDD I IleakageleakageDynamic power(~90% today anddecreasingrelatively)Short-circuitpower(~8% today anddecreasingabsolutely)Leakage power(~2% today andincreasing) f0→1 = P0→1 * fclockECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPower and Energy Design SpacePower and Energy Design Space + Variable V + Variable VTTSleep TransistorsSleep TransistorsMulti-Multi-VVddddVariable VVariable VTT+ Multi-V+ Multi-VTTLeakageLeakageDFS, DVSDFS, DVS(Dynamic(DynamicFreq, VoltageFreq, VoltageScaling)Scaling)Clock GatingClock GatingLogic DesignLogic DesignReduced Reduced VVddddSizingSizingMulti-Multi-VVddddActiveActiveRun TimeRun TimeNon-active ModulesNon-active ModulesDesign TimeDesign TimeEnergyEnergyVariableVariableThroughput/LatencyThroughput/LatencyConstantConstantThroughput/LatencyThroughput/LatencyECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutBus MultiplexingBus Multiplexing••Share long data buses with time multiplexing (SShare long data buses with time multiplexing (S11 uses even uses even cycles, S cycles, S22odd)odd)S2S1D1D2S1S2D2D1••Buses are a significant source of power dissipation due to high switchingBuses are a significant source of power dissipation due to high switchingactivities and large capacitive loadingactivities and large capacitive loading––15% of total power in Alpha 2106415% of total power in Alpha 21064––30% of total power in Intel 8038630% of total power in Intel 80386••But what if data samples are correlated (e.g., sign bits)?But what if data samples are correlated (e.g., sign bits)?ECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutCorrelated Data StreamsCorrelated Data Streams00.5114 12 10 8 6 4 2 0MuxedDedicatedBit positionMSBLSBBit switching probabilities••For a shared (multiplexed) busFor a shared (multiplexed) busadvantages of data correlationadvantages of data correlationare lost (bus carries samplesare lost (bus carries samplesfrom two uncorrelated datafrom two uncorrelated datastreams)streams)––Bus sharing should not beBus sharing should not beused for used for positivelypositivelycorrelated data streamscorrelated data streams––Bus sharing may proveBus sharing may proveadvantageous in aadvantageous in anegativelynegatively correlated data correlated datastream (where successivestream (where successivesamples switch sign bits) -samples switch sign bits) -more random switchingmore random switchingECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutGlitch Reduction by PipeliningGlitch Reduction by Pipelining••Glitches depend on the Glitches depend on the logic depthlogic depth of the circuit - gates deeper in of the circuit - gates deeper inthe logic network are more prone to the logic network are more prone to glitchingglitching––arrival times of the gate inputs are more spread due to delayarrival times of the gate inputs are more spread due to delayimbalancesimbalances––usually affected more by primary input switchingusually affected more by primary input switching••Reduce logic depth by adding pipeline registersReduce logic depth by adding pipeline registers––additional energy used by the clock and pipeline registersadditional energy used by the clock and pipeline registersPCFetch Decode Execute Memory WriteBackInstructionMARMDRI$ D$clkpipelinestageisolationregisterECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPower and Energy Design SpacePower and Energy Design Space + Variable V + Variable VTTSleep TransistorsSleep TransistorsMulti-Multi-VVddddVariable VVariable VTT+ Multi-V+ Multi-VTTLeakageLeakageDFS, DVSDFS, DVS(Dynamic(DynamicFreq, VoltageFreq, VoltageScaling)Scaling)Clock GatingClock GatingLogic DesignLogic DesignReduced Reduced VVddddSizingSizingMulti-Multi-VVddddActiveActiveRun TimeRun TimeNon-active ModulesNon-active ModulesDesign TimeDesign TimeEnergyEnergyVariableVariableThroughput/LatencyThroughput/LatencyConstantConstantThroughput/LatencyThroughput/LatencyECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock GatingClock Gating••Gate off clock to idle functional unitsGate off clock to idle functional units––e.g., floating point unitse.g., floating point units––need logic to generateneed logic to generatedisabledisable signal signal••increases complexity of control logicincreases complexity of control logic••consumes powerconsumes power••timing critical to avoid clock glitchestiming critical to avoid clock glitchesat OR gate outputat OR gate output––additional gate delay on clock signaladditional gate delay on clock signal••gating OR gate can replace a buffer ingating OR gate can replace a buffer inthe clock distribution treethe clock distribution tree••Most popular method for power reduction of clock signals andMost popular method for power reduction of clock signals andfunctional unitsfunctional unitsRegclockdisableFunctionalunitECE 249 VLSI Design and SimulationSpring 2005Lecture 20© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock Gating in a Pipelined Clock Gating in a Pipelined DatapathDatapath••For idle units (e.g., floating point units in Exec stage, WBFor idle units (e.g., floating point units in Exec stage, WBstage for