ECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutTopicsTopics––Design StrategiesDesign StrategiesParts of this lecture were adapted from “Digital Integrated Circuits” Rabaey et al. Copyright 2003 Prentice Hall/PearsonECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutStandard Cell LibrariesStandard Cell Libraries••How do you decide on the composition ofHow do you decide on the composition ofthe cell librarythe cell library??––Number of inputsNumber of inputs––Transistor sizing for varying capacitive loadsTransistor sizing for varying capacitive loads––PullupPullup//pulldown pulldown ratioratioECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutStandard Cell LibrariesStandard Cell LibrariesECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutStandard Cell LibrariesStandard Cell LibrariesECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutStandard Cell LibrariesStandard Cell LibrariesECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutCompiled CellsCompiled Cells••Standard cellsStandard cells––Must be redesigned for every new processMust be redesigned for every new processtechnologytechnology––Design options are limited because of discrete set ofDesign options are limited because of discrete set ofcellscells••Customized cells would provide more flexibilityCustomized cells would provide more flexibility––Automatic layout generation for design-specificAutomatic layout generation for design-specificrequirementsrequirementsECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutAutomatic CellAutomatic Cell Generation GenerationCourtesy AcadabraInitial transistorgeometriesPlacedtransistorsRoutedcellCompactedcellFinishedcellECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMacrocellsMacrocells••Hard MacrosHard Macros––Predetermined physical designPredetermined physical design––Fixed transistor and wiring locationsFixed transistor and wiring locations––Dense layout, optimized performance andDense layout, optimized performance andpower characteristicspower characteristicsECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutCell-based DesignCell-based Design (or standard cells) (or standard cells)Routing channelrequirements arereduced by presenceof more interconnectlayersFunctionalmodule(RAM,multiplier,…)RoutingchannelLogic cellFeedthrough cellECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMacrocellsMacrocells256×32 (or 8192 bit) SRAMGenerated by hard-macro module generatorECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMacrocellsMacrocells••Soft MacrosSoft Macros––Physical design is done automaticallyPhysical design is done automatically––Easily ported across many differentEasily ported across many differenttechnologies and processestechnologies and processes––Macro cell compiler will take a functional andMacro cell compiler will take a functional andparameterized description and generate aparameterized description and generate anetlist netlist of standard cellsof standard cellsECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMacrocellsMacrocellsECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutIntellectual propertyIntellectual property••Macrocells Macrocells can be can be aquired aquired from third-partyfrom third-partyvendorsvendors––Includes appropriate compilers, debuggers,Includes appropriate compilers, debuggers,test vectors, prediction modelstest vectors, prediction models––Similar to reusable software librariesSimilar to reusable software libraries––Examples include embedded processors,Examples include embedded processors,bus interfaces, DSP processors, ECCbus interfaces, DSP processors, ECCcoders, MPEG coders, MPEG codecscodecs, etc., etc.ECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of Connecticut““Intellectual PropertyIntellectual Property””A Protocol Processor for WirelessECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutSemicustomSemicustom Design Flow Design FlowHDLHDLLogic SynthesisLogic SynthesisFloorplanningFloorplanningPlacementPlacementRoutingRoutingTape-outCircuit ExtractionCircuit ExtractionPre-LayoutSimulationPre-LayoutSimulationPost-LayoutSimulationPost-LayoutSimulationStructuralStructuralPhysicalPhysicalBehavioralBehavioralDesign CaptureDesign IterationDesign IterationECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutIntegrating Synthesis withIntegrating Synthesis withPhysicalPhysical Design DesignPhysical SynthesisPhysical SynthesisRTL (Timing) ConstraintsPlace-and-RouteOptimizationPlace-and-RouteOptimizationArtworkNetlist with Place-and-Route InfoMacromodulesFixed netlistsECE 249 VLSI Design and SimulationSpring 2005Lecture 19© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutSystem-on-a-Chip (SoC) DesignSystem-on-a-Chip (SoC) Design••Embed multiple functionalities on a singleEmbed multiple functionalities on a singlechipchip••SoC is a natural result of having more andSoC is a natural result of having more andmore transistors availablemore transistors available••Managing multiple modules becomes aManaging