ECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutTopicsTopics••Layout StylesLayout Styles••Layout StrategiesLayout StrategiesECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of Connecticut3D Perspective3D PerspectivePolysiliconAluminumECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutDesign RulesDesign Rules••Interface between designer and process engineerInterface between designer and process engineer••Guidelines for constructing process masksGuidelines for constructing process masks••Unit dimension: Minimum line widthUnit dimension: Minimum line width––scalable design rules: lambda parameterscalable design rules: lambda parameter––absolute dimensions (micron rules)absolute dimensions (micron rules)ECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutCMOS Process LayersCMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)GreenECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayers in 0.25 Layers in 0.25 µµm CMOSm CMOSprocessprocessECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout StylesLayout Styles••Horizontal flow (vertical transistors)Horizontal flow (vertical transistors)VDDVOUTVSSVINECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout StylesLayout Styles••Horizontal flow (horizontal transistors)Horizontal flow (horizontal transistors)ECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout StylesLayout Styles••Vertical flow (horizontal transistors)Vertical flow (horizontal transistors)••Standard cell designStandard cell designECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutWiring TracksWiring Tracks••A A wiring trackwiring track is the space required for a wire is the space required for a wire––4 4 λλ width, 4 width, 4 λλ spacing from neighbor = 8 spacing from neighbor = 8 λλ pitch pitch••Transistors also consume one wiring trackTransistors also consume one wiring trackECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutWell spacingWell spacing••Wells must surround transistors by 6 Wells must surround transistors by 6 λλ––Implies 12 Implies 12 λλ between opposite transistor flavors between opposite transistor flavors––Leaves room for one wire trackLeaves room for one wire trackECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutArea EstimationArea Estimation••Estimate area by counting wiring tracksEstimate area by counting wiring tracks––Multiply by 8 to express in Multiply by 8 to express in λλECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutExample: O3AIExample: O3AI()YABCD=++ECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategies••How do you decide on a layout?How do you decide on a layout?––Area constraintsArea constraints––Requirements of inputs and outputsRequirements of inputs and outputs––Metal layer interconnectMetal layer interconnect––Difficult for multi-input gatesDifficult for multi-input gates••How do you decide on order of inputs?How do you decide on order of inputs?ECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategies••Euler path methodEuler path method••Convert schematic into a graphConvert schematic into a graph••EgEg. F=AB+C+DE. F=AB+C+DEAEDCBABCDEECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategiesA BCD EADCBEECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategiesA BCD EABCDE•Find common path in both graphs (Euler path)•A to B to C to D to EECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategiesAB C D E FECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategies••Euler path methodEuler path method––Not always guaranteed to find a Euler pathNot always guaranteed to find a Euler path––For example, if the function wasFor example, if the function wasF=C+AB+DEF=C+AB+DE––If no Euler path found, you will need to breakIf no Euler path found, you will need to breakthe the gate, or rearrange the inputsgate, or rearrange the inputsECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategies••How do you decide on a layout?How do you decide on a layout?––Area constraintsArea constraints––Requirements of inputs and outputsRequirements of inputs and outputs––Metal layer interconnectMetal layer interconnect––Performance considerationsPerformance considerationsECE 249 VLSI Design and SimulationSpring 2005Lecture 10© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLayout strategiesLayout strategies••Very wide transistorsVery wide
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