VLSI Design and SimulationVLSI Design and SimulationLecture Lecture 55Performance CharacterizationPerformance CharacterizationECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutTopicsTopics••PerformancePerformance Characterization Characterization––Resistance EstimationResistance Estimation––Capacitance EstimationCapacitance Estimation––Inductance EstimationInductance EstimationECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPerformance CharacterizationPerformance CharacterizationVinVoutVDDVDD••Inverter Voltage Transfer CurveInverter Voltage Transfer CurveECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPerformance CharacterizationPerformance Characterization••Voltage versus Time curve (ideal)Voltage versus Time curve (ideal)timeVDDVinVoutECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPerformance CharacterizationPerformance Characterization••Gate delayGate delay••Voltage Voltage versus Time curveversus Time curvetimeVDDVoutVinECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPerformance CharacterizationPerformance Characterization••Interconnect delayInterconnect delaytimeVDDV1V2V1V2ECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPerformance CharacterizationPerformance Characterization••DelayDelay––Primary determinant of the speed of a circuitPrimary determinant of the speed of a circuit––Due to resistances and capacitancesDue to resistances and capacitances••Intrinsic resistance and capacitanceIntrinsic resistance and capacitance••Extrinsic resistance and capacitanceExtrinsic resistance and capacitanceECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutResistance EstimationResistance Estimation••Dependent on Dependent on resistivityresistivity of material of material••Directly proportional to lengthDirectly proportional to length••Inversely proportional to cross-sectionalInversely proportional to cross-sectionalareaarea€ R =ρlAECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutResistance EstimationResistance Estimation€ R =ρLA=ρHLW= RSLWHWLECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutResistance EstimationResistance EstimationHWL••RRSS is the sheet resistance expressed in is the sheet resistance expressed interms of terms of ΩΩ//H2W2LECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutResistance EstimationResistance Estimation50-15050-150DiffusionDiffusion150-200150-200PolysiliconPolysilicon00..005-0.15-0.1Top metalTop metalTypical Resistance (Typical Resistance (ΩΩ//))Interconnect MaterialInterconnect MaterialECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutResistance EstimationResistance Estimation••Intrinsic resistanceIntrinsic resistance••In linear regionIn linear region€ IDS= k VGS−VT( )VDS−VDS22      Req=1k VGS−VT( )=1µCoxWLVGS−VT( )=1µCoxVGS−VT( )LWRS=1µCoxVGS−VT( )ECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutResistance EstimationResistance Estimation••Intrinsic resistanceIntrinsic resistance––Dependent on CDependent on Coxox and carrier mobility and carrier mobility––Temperature variantTemperature variant––Typically 1000-30000 Typically 1000-30000 ΩΩ//ECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutCapacitance EstimationCapacitance Estimation••Capacitance in concert with interconnectCapacitance in concert with interconnectresistance is the primary determinant ofresistance is the primary determinant ofinterconnect delaysinterconnect delays••Intrinsic capacitanceIntrinsic capacitance••Interconnect capacitancesInterconnect capacitancesECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMOS device capacitancesMOS device capacitances••Overlap related capacitanceOverlap related capacitance••Channel related capacitancesChannel related capacitances––Dependent on region of operationDependent on region of operation••Diffusion to substrate capacitancesDiffusion to substrate capacitancesECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMOS device capacitancesMOS device capacitancesSourceGaten+n+DrainCDBCGDOCGCBCGSOCSBCGCDCGCSECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMOS device capacitancesMOS device capacitancesCGCDCGCSCGCBCSBCDBECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMOS device capacitancesMOS device capacitances••Overlap related capacitanceOverlap related capacitance••Usually can be ignored since Usually can be ignored since xxDD is very is verysmallsmall€ CGSO= CDSO=εoxtoxAoverlap= CoxxDWECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutMOS device capacitancesMOS device capacitances••Channel related capacitancesChannel related capacitances––CutoffCutoff••No channelNo channel••Therefore, no gate to source or drain capacitancesTherefore, no gate to source or drain capacitancesECE 249 VLSI Design and SimulationSpring 2005Lecture 5© John A.