ECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutTopicsTopics••Performance CharacterizationPerformance Characterization––Interconnect DelayInterconnect Delay––Gate DelayGate Delay––Switching Switching CharacteristicsCharacteristicsECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect delayInterconnect delay•Lumped RC modelVinVout•Charge Vin to VDD•The transient output voltage is€ Vout(t) = VDD1− e−tRC      € VDD2= VDD1− e−tdlhRC      tdlhRC= −ln12      tdlh≈ .69RCRCECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect delayInterconnect delay•Distributed RC ladder modelVinVoutC/N C/N C/N C/NR/N R/N R/N R/N•More accurate than lumped RC model•More difficult to solve for large N•Need full-scale SPICE simulationECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutElmore DelayElmore Delay••Single line model not useful forSingle line model not useful forgeneralized RC tree networksgeneralized RC tree networksVinC1C2C3C4R1R2R3R4ECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutElmore DelayElmore Delay••First order calculation of time constant ofFirst order calculation of time constant ofthe circuitthe circuit€ td= CjRkk ∈ path∑j=1N∑VinC1C2C3C4R1R2R3R4€ td 3= R1C1+ R1+ R2( )C2+ R1+ R2+ R3( )C3+ R1C4td 4= R1C1+ R1C2+ R1C3+ R1+ R4( )C4ECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutElmore DelayElmore Delay€ td= CjRkk ∈ path∑j=1N∑VinC1C2C3C4R1R2R3R4€ td 3= R1C1+ C2+ C3+ C4( )+ R2C2+ C3( )+ R3C3td 4= R1C1+ C2+ C3+ C4( )+ R4C4ECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutElmore DelayElmore DelayVinVoutC/N C/N C/N C/NR/N R/N R/N R/N€ td=CNRNk=1j∑j=1N∑=CNRNN N +1( )2= RCN +12N      € td=RC2€ N → ∞forECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay€ td= 8Ω 20 fF + 10 fF( )+ 4Ω 10 fF( )= .28 ps10fF4ΩVin8Ω20fFECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect DelayVin10fF8Ω4Ω€ td= 8Ω 20 fF + 10 fF + 10 fF + 10 fF( )+ 4Ω 10 fF( )= .44 ps10fF10fF20fF4Ω4ΩECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay••Fanout Fanout EffectsEffects––Lines with multiple loads will have longer delaysLines with multiple loads will have longer delays••ClocksClocks••Data busesData buses••Control linesControl lines––SolutionsSolutions••Wider and thicker lines for special signalsWider and thicker lines for special signals••Buffer driversBuffer driversECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect DelayVinVoutC/N C/N C/N C/NR/N R/N R/N R/N€ td=CNRNk=1j∑j=1N∑=CNRNN N + 1( )2= RCN + 12N      € td=RC2€ N → ∞forECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay€ td=RC2=12rlw      calw + cpl + w( )( )≈12rcal2••Delay is proportional to the square of theDelay is proportional to the square of thelengthlength••Try to avoid long linesTry to avoid long linesECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay5000µ metal1 (0.5µ wide)•Interconnect resistance•Interconnect capacitance•Intrinsic load capacitance€ R = .075000µ0.5µ= 700Ω€ Cwire= .03 ⋅ 5000µ⋅ 0.5µ+ .044 ⋅ 2 ⋅ 5000µ+ 0.5µ( )= 515 fF•Propagation delay€ tp=RCwire2+ RCin=700 ⋅ 515 fF2+ 700 ⋅ 5 fF = 184 ps€ Cin≈ 5 fFECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay••Avoid long interconnect delays using buffersAvoid long interconnect delays using buffers2500µ metal1 (0.5µ wide)•Interconnect resistance•Interconnect capacitance•Intrinsic load capacitance€ R = .072500µ0.5µ= 350Ω€ Cwire= .03 ⋅ 2500µ⋅ 0.5µ+ .044 ⋅ 2 ⋅ 2500µ+ 0.5µ( )= 258 fF•Propagation delay€ tp= 2 ⋅RCwire2+ RCin      = 2 ⋅350 ⋅ 258 fF2+ 350 ⋅ 5 fF      = 94 ps2500µ metal1 (0.5µ wide)€ Cin≈ 5 fFECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay••Avoid long interconnect delays using widerAvoid long interconnect delays using widerlineslines5000µ metal1 (5µ wide)•Interconnect resistance•Interconnect capacitance•Intrinsic load capacitance€ R = .075000µ5µ= 70Ω€ Cwire= .03 ⋅ 5000µ⋅ 5µ+ .044 ⋅ 2 ⋅ 5000µ+ 5µ( )= 1190 fF€ Cin≈ 5 fF•Propagation delay€ tp=RCwire2+ RCin=70 ⋅1190 fF2+ 70 ⋅ 5 fF = 42 psECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect delayInterconnect delay••Interconnect sizingInterconnect sizing––Adjust delaysAdjust delays––Prevent metal migrationPrevent metal migration––Power supply noise and signal integrityPower supply noise and signal integrityECE 249 VLSI Design and SimulationSpring 2005© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutInterconnect DelayInterconnect Delay€ td= 2Ω 20 fF + 10 fF( )+ 4Ω 10 fF( )= .10 ps10fF4ΩVin2Ω20fF500µ500µ1µ2µRS=.08 Ω/Ca=.02 fF/µ2€ td= 4Ω 10 fF + 20 fF( )+ 2Ω 20 fF( )= .16