ECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutTopicsTopics––ClockingClockingParts of this lecture were adapted from “Digital Integrated Circuits” Rabaey et al. Copyright 2003 Prentice Hall/PearsonECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutFinite State MachineFinite State MachineLogicMemoryCurrent StateNext StateInputs OutputsECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutSynchronous TimingSynchronous TimingCombinationalLogicR1R2CinCout OutInCLKECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutRegister DesignRegister DesignCLKCLKABXDQCLKCLKECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutRegister DesignRegister Design••Inverted clock is not idealInverted clock is not ideal••Causes delays on the clockCauses delays on the clock••Overlapping clock pairOverlapping clock pairECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutRegister DesignRegister DesignCLKCLKAB(a) Schematic diagram(b) Overlapping clock pairsXDQCLKCLKCLKCLKECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutRegister DesignRegister Design••Use non-overlapping clocksUse non-overlapping clocksPH1PH1ABXDQPH2PH2PH2PH1ECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutRegister DesignRegister Design••Generating non-overlapping clocksGenerating non-overlapping clocksPH1PH2CLKECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutLatch ParametersLatch ParametersDClkQDQClktc-qtholdPWmtsutd-qTECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutRegister ParametersRegister ParametersDClkQDQClktc-qtholdTtsuECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock Clock NonidealitiesNonidealities••Clock SkewClock Skew––Spatial variations in equivalent clock edgesSpatial variations in equivalent clock edges––Mostly deterministicMostly deterministic••Clock JitterClock Jitter––Temporal variations in consecutive clock edgesTemporal variations in consecutive clock edges––Mostly randomMostly random••Pulse Width VariationPulse Width VariationECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock Skew and JitterClock Skew and JitterClkClktSKtJS••Skew and jitter can affect the cycle timesSkew and jitter can affect the cycle times••Clock skew can cause race conditionsClock skew can cause race conditionsECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock UncertaintiesClock Uncertainties243Power SupplyInterconnect5 Temperature6 Capacitive Load7 Coupling to Adjacent Lines1 Clock GenerationDevicesECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock UncertaintiesClock Uncertainties••Clock Signal GenerationClock Signal Generation––Analog circuit sensitive to noiseAnalog circuit sensitive to noise––Causes jitterCauses jitter––Difficult to modelDifficult to model••Device ManufacturingDevice Manufacturing––Process variationsProcess variations––Causes static skewCauses static skew––Can be partially modeledCan be partially modeledECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock UncertaintiesClock Uncertainties••Interconnect variationsInterconnect variations––Causes skew on different pathsCauses skew on different paths––Different inter-layer dielectric thicknessDifferent inter-layer dielectric thickness––Can be somewhat predictable based on processCan be somewhat predictable based on process••TemperatureTemperature––Dependent on switching activityDependent on switching activity––Parts of a chip may see different temperaturesParts of a chip may see different temperatures––Contributes to clock jitterContributes to clock jitterECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutClock UncertaintiesClock Uncertainties••Power supply variationsPower supply variations––Dependent on switching Dependent on switching activiityactiviity––Causes jitterCauses jitter••Capactive Capactive couplingcoupling––Between clock and adjacent linesBetween clock and adjacent lines––Transitions on adjacent lines can cause varyingTransitions on adjacent lines can cause varyingcoupling effectscoupling effects––Net effect is jitter on the clockNet effect is jitter on the clockECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPositive and Negative SkewPositive and Negative SkewR1In(a) Positive skewCombinationalLogicD QtCLK1CLKdelaytCLK2R2D QCombinationalLogictCLK3R3• • •D QdelayR1In(b) Negative skewCombinationalLogicD QtCLK1delaytCLK2R2D QCombinationalLogictCLK3R3• • •D QECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutPositive SkewPositive SkewCLK1CLK2TCLKTCLK++ th214Launching edge arrives before the receiving edgeECE 249 VLSI Design and SimulationSpring 2005Lecture 17© John A. ChandyDept. of Electrical and Computer EngineeringUniversity of ConnecticutNegative SkewNegative SkewCLK1CLK2TCLKTCLK +2143Receiving edge arrives before the launching edgeECE 249 VLSI Design and SimulationSpring