VLSI Design and Simulation Lecture 3 CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter First Order DC Analysis V DD V DD Rp V out V out VOL 0 VOH VDD Rn Vin 0 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vin VDD John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter Transient Response V DD V DD tpHL f R on CL Rp 0 69 RonCL V out V out CL CL Rn Vin 0 a Low to high ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vin VDD b High to low John A Chandy Dept of Electrical and Computer Engineering University of Connecticut PMOS Load Lines IDn V in V DD VGSp IDn IDp V out VDD VDSp V out IDp Vin 0 IDn IDn Vin 1 5 VGSp 1 VGSp 2 5 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 V DSp Vin V DD VGSp IDn IDp Vin 0 Vin 1 5 V DSp Vout Vout V DD VDSp John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter Load Characteristics I Dn PMOS Vin 0 Vin 2 5 Vin 0 5 Vin 2 Vin 1 Vin 1 5 Vin 1 5 Vin 2 Vin 2 5 NMOS Vin 1 Vin 1 5 Vin 1 Vin 0 5 Vin 0 Vout ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout NMOS off PMOS res 5 2 NMOS sat PMOS res 2 NMOS sat PMOS sat 5 1 1 NMOS res PMOS sat 5 0 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 0 5 1 1 5 2 NMOS res PMOS off 2 5 Vin John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC nMOS cutoff pMOS linear Vout VDD Vtn ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vin John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout nMOS saturation pMOS linear VDD Vtn ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vout Vtp Vin John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Set pMOS Linear IDS equal to nMOS Saturation IDS 2 V V 2 Vout VDD in tn k p Vin VDD Vtp Vout VDD kn 2 2 Vout VDD 2 2 k V Vtn Vin VDD Vtp Vout VDD n in 0 kp 2 2 Vout VDD Vin VDD Vtp Vin VDD Vtp Vout Vin Vtp 2 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 2 Vin VDD Vtp kn 2 Vin Vtn kp kn 2 Vin Vtn kp John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Short channel model 2 Vout VDD VDSATn k nVDSATn Vin Vtn k p Vin VDD Vtp Vout VDD 2 2 Vout VDD 2 2 Vin VDD Vtp Vout VDD Vout VDD Vin VDD Vtp Vout Vin Vtp ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 V kn V VDSATn Vin Vtn DSATn 0 kp 2 2 Vin VDD Vtp 2 2 in VDD Vtp 2 kn V VDSATn Vin Vtn DSATn kp 2 kn V VDSATn Vin Vtn DSATn kp 2 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout VDD nMOS saturation pMOS saturation Vtn Vin Vout Vtp ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vout Vtn John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout VDD nMOS linear pMOS saturation Vtn VDD Vtp Vout Vtp ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vin Vout Vtn John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Set nMOS Linear IDS equal to pMOS Saturation IDS 2 2 V V V Vout in DD tp kp k V Vtn Vout n in 2 2 2 2 k p Vin VDD Vtp Vout Vin Vtn Vout 0 2 kn 2 Vout Vin Vtn ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vin Vtn 2 kp 2 Vin VDD Vtp kn John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Short channel model VDSATp Vout 2 k pVDSATp Vin VDD Vtp k n Vin Vtn Vout 2 2 k V Vout 2 Vin Vtp Vout p VDSATp Vin VDD Vtp DSATp 0 2 kn 2 Vout Vin Vtn Vin Vtn 2 VDSATp 2 VDSATp Vin VDD Vtp kn 2 kp ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout VDD nMOS linear pMOS cutoff Vtn VDD Vtp Vout Vtp ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vout Vtn Vin VDD John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout VDD Vtn VDD Vtp Vin VDD ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter Vin pMOS mode nMOS mode Vout Vin Vt Linear Cutoff VDD Vt Vin Vout Vt Linear Saturation Vout Vt Vin Vout Vt Saturation Saturation Saturation Linear Vin Vt Vin Vt Cutoff Linear 0 Vout Vt Vin VDD Vt Vin VDD Vt ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vin Vt Vin VDD Vt 2 Vin Vt 2 Interpolate 2 Vin VDD Vt 2 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut Switching Threshold The point at which the inverter has both transistors in saturation kp 2 kn 2 VM Vtn VM VDD Vtp 2 2 k p V V VM VDD Vtp M tn kn VM 1 r Vtn r VDD Vtp VM ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 Vtn r VDD Vtp 1 r John A Chandy Dept of Electrical and Computer Engineering University of Connecticut Switching Threshold VM r VDD Vtp Vtn 1 r When Vtn Vtp and r 1 VM VDD 2 In switching region the curve is actually vertical V out can have multiple values ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut CMOS Inverter VTC Vout VDD VM Vtp VM Vtp Vtn VM VDD Vtp Vin VDD ECE 249 VLSI Design and Simulation Spring 2005 Lecture 3 John A Chandy Dept of Electrical and Computer Engineering University of Connecticut Switching Threshold With short channel devices VDSATp VDSATn knVDSATn VM Vtn k pVDSATp VM VDD Vtp 2 2 k pVDSATp VDSATp VDSATn VM Vtn VM VDD Vtp 2 k nVDSATn 2 k pVDSATp VDSATp VDSATn k pVDSATp VM 1 Vtn VDD Vtp 2 knVDSATn 2 k nVDSATn VDSATp VDSATn Vtn r VDD …