Analog Devices Incorporated BlackfinNote on this presentation seriesIntroductionIntroductionIntroductionInstruction SetData Registers and AccumulatorsHalf-word accessPointer RegistersInstruction Set - PointersSpecial RegistersInstruction Set – Special RegsInstruction Set - AddressingInstruction Set - LogicalInstruction Set - ArithmeticInstruction Set - ArithmeticInstruction Set – Op FlagsInstruction Set – Flow ControlHardware Loop RegistersInstruction Set - LoopsInstruction Set - ConditionalsInstruction Set – Shift/RotateInstruction Set – Bit OpsInstruction Set – Pixel OpsInstruction Set – Vector OpsInstruction Set – Parallel IssueInstruction Set - InterruptsInstruction Set –Cache ControlInstruction Set - EncodingInstruction Set – Code SampleInstruction Set – Code SampleBF533 Block DiagramBlackfin CoreProcessorProcessor – Bus HierarchyProcessor – Bus HierarchyBF561 Dual Core Block Diagram Processor – Operating ModesProcessor – Mode ChangeProcessor PipelineProcessor PipelineMemoryMemoryMemoryBF533 Memory MapPeripheralsPeripheralsPhysical PackagingPhysical Packaging - PinoutsSoftware ToolsApplicationsApplicationsApplicationsRoadmap for Future ReleasesResourcesCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 1Analog Devices IncorporatedBlackfinCS 433Prof. Luddy HarrisonProcessor Presentation SeriesCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 2Note on this presentation seriesz These slide presentations were prepared by students of CS433 at the University of Illinois at Urbana-Champaignz All the drawings and figures in these slides were drawn by the students. Some drawings are based on figures in the manufacturer’s documentation for the processor, but none are electronic copies of such drawingsz You are free to use these slides provided that you leave the credits and copyright notices intactCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 3Introductionz Blackfin combines 16-bit fixed point DSP features with general purpose microcontroller functions, eliminating the need for two processors in many applications.z Design provides a balance between DSP performance, low power and low cost.z First product to use the Micro Signal Architecture jointly developed by Analog Devices and Intel.CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 4Introductionz Targets embedded audio, video and communications applications.z First generation BF535 released in 2001z Second (current) generation has 5 members:z Single core BF531/BF532/BF533 from $4.95z Dual core BF561 from $19.95 (prices @10K units)z msp500 SoftFone for GSM/GPRS/EDGEz Dual ALUs and 16x16 multipliers per coreCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 5Introductionz 32-bit RISC Instruction Set w/3 issue VLIWz 64 bits: up one 32-bit and two 16-bit instructionsz 10-stage fully interlocked pipelinez On-chip memory can be cache or data SRAMz Integrates microcontroller style peripheralsz Wide range of speeds/voltagesz From 100 MHz/0.7 V to 750 MHz/1.4 Vz Supervisor and User modes for protectionCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 6Instruction Setz Algebraic assembly languagez Ease of coding and readabilityz Optimized for C/C++ compilationz Orthogonal instruction setz Encoding assigns 16-bit op-codes to frequently use instructions. Complex DSP and arithmetic instructions are encoded into 32-bit op-codes.CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 7Data Registers and AccumulatorsCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 8Half-word accessz Data registerscan be accessedby half words (high, low)z R0 = R1;z R3 = 0x7F11;z R8.H = R7.L;z R3.H = R2.L;CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 9Pointer RegistersCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 10Instruction Set - Pointersz Load/Store to Data or Pointer RegR3 = [P0++];P3 = [P2];[--P5] = R4;z Push/Pop Single or Multiple Regs[--SP] = R2;[--SP] = (R7:4, P5:3); (R7:4, P5:3) = [SP++];R2 = [SP++];CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 11Special RegistersCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 12Instruction Set – Special Regsz Index and ModifySpecial Purpose Registersz i Regs: Data structuresz m Reg: Offsetz Commonly used forcircular buffersi0 += m0;i1 += m1 (brev);CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 13Instruction Set - Addressingz Register IndirectR3 = [P3];z Register indirect w/post increment/decrementR3 = [P3++];z Register indirect indexed with offsetR6 = [P2 + 12];z Register indirect with pre-decrement (push)[--SP] = R2;z Register indirect with post-increment (pop)R2 = [SP++];CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 14Instruction Set - Logicalz & - Logical ANDR3 = R3 & R2;z | - Logical ORz ^ - Logical XOR (Exclusive ORz ~ - Logical NOT (One’s complement)r5 = ~ r6;z BXORSHIFT - Four Bit XOR w/Shiftr0.l = cc = bxorshift(a0, r1);CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 15Instruction Set - Arithmeticz AddR3 = R1 + R2;z SubtractP2 = P1 – P0;z Minimum / Maximumr5 = min(r2, r3);z MultiplyR3.L = R3.H * R2.H;r6 = r3.h * r4.h; /* 32 bit result */R3 *= R0; /* 32 bit multiply */CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 16Instruction Set - Arithmeticz Multiply/Accumulate (to Accumulator register)A0 += R3.H * R2.H;z DivideDIVS(dividend_reg, divisor_reg);DIVQ(dividend_reg, divisor_reg);z As with many fixed point DSPs, many math operations support operation flags (covered below) to saturate or truncate, as well as to define fractional or integer operations.CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 17Instruction Set – Op Flagsz Operation Flags(S) Saturate (NS) No saturation;(IS) Signed Integer (IU) Unsigned Integer(IH) Signed Integer, high word extract(ISS2) Signed integer with scaling(FU) Unsigned Fraction 0.16 * 0.16 Æ 0.32(TFU) Unsigned Fraction with truncation(T) Signed Frac. w/Trunc 1.15 * 1.15 Æ 1.31(S2RND) Signed fraction with scaling and rounding(M) Mixed mode multiply (BREV) Carry bit reverseR0 = R5 - R3 (NS);A1 = R0.H * R0.L (M);CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 18Instruction Set – Flow Controlz JUMP – Load program counter with target addressjump (p2); /* p2 contains target address */jump (pc + p2); /* relative to program counter */jump next_section; /*