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U of I CS 433 - LECTURE NOTES

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CS433: Computer System OrganizationHistory8086 / 8088 (1978)Intel 286 (1982)Intel 386 (1985)Intel 486 (1989)Intel Pentium (1993)Intel P6 (1995 – 1999)Pentium ProPentium IIPentium II XeonCeleronPentium IIIPentium III XeonPentium 4 (2000)Pentium 4 Supporting Hyper-Threading Technology (2004)Intel Xeon (2001-2004)Intel Pentium M (2003)NetBurst MicroArchitecture (Pentium 4)Front-End PipelineInstruction LayoutIA32 Instruction FormatRegistersSpecial Register PurposesOverlaid RegistersEFLAGSSystem Status in EFLAGSData TypesFundamental Data TypesFloating Point TypesIEEE 754 and IA32Example of Semantic Difference Between Natural x86 Execution and C SemanticsOperating on NaNsPointer TypesDisadvantages of Far Pointers?SIMDMMX Types (64-bits)BCD (Binary Coded Decimal)MemoryMemory ModelsSegment SelectorsSeg Regs in Flat Mem ModelSegmented Memory ModelConstructing an AddressDefault SegmentsOffset CalculationFlat ModelSystem Table RegistersProtected Flat ModelMulti-Segment Model11/29/2005 CS433 Luddy Harrison 1CS433: Computer System OrganizationLuddy HarrisonIntel IA32 Architecture11/29/2005 CS433 Luddy Harrison 2HistoryThe x86 / IA32 family11/29/2005 CS433 Luddy Harrison 38086 / 8088 (1978)z 16-bit registersz 16-bit external data bus (8086)z 8-bit external data bus (8088)z 20-bit address space via segment registers11/29/2005 CS433 Luddy Harrison 4Intel 286 (1982)z segment registers point to descriptor tablesz descriptors have 24-bit segment addressesz segment swappingz protectionz bounds checking on segmentsz read/execute/write checkingz four privelege levels11/29/2005 CS433 Luddy Harrison 5Intel 386 (1985)z 32-bit registers (data and address)z virtual 8086 modez 32-bit address busz segmented memory model + flat memory modelz paging with 4Kbyte pagesz pipelined execution (decode + execution)11/29/2005 CS433 Luddy Harrison 6Intel 486 (1989)z five stage pipelinez 8Kb on-chip L1 cachez write-throughz integrated x87 FPUz power management11/29/2005 CS433 Luddy Harrison 7Intel Pentium (1993)z two pipelines, u and vz superscalar executionz 8kb data + 8kb instruction on-chip L1 cachesz write-back option in addition to write-throughz branch predictionz burstable 64-bit external data busz multiprocessor supportz [second stepping: MMX]11/29/2005 CS433 Luddy Harrison 8Intel P6 (1995 – 1999)z Pentium Proz Pentium IIz Pentium II Xeonz Celeronz Pentium IIIz Pentium III Xeon11/29/2005 CS433 Luddy Harrison 9Pentium Proz 3-way superscalarz out-of-orderz more aggressive branch predictionz speculative executionz L1 + L2 cache on chipz 8K + 8K L1z 256K L211/29/2005 CS433 Luddy Harrison 10Pentium IIz MMX (in P6 family)z 16K + 16K L1 cachesz 256K, 512K, 1M L2 caches supportedz improved power management11/29/2005 CS433 Luddy Harrison 11Pentium II Xeonz improved multiprocessor supportz 4- and 8-way systemsz 2Mb L2 cache on chip11/29/2005 CS433 Luddy Harrison 12Celeronz low-priced / reduced power marketz 128K L2 cachez cheaper package (plastic)11/29/2005 CS433 Luddy Harrison 13Pentium IIIz Streaming SIMD Extensions (SSE)z 128-bit registersz floating point vector types11/29/2005 CS433 Luddy Harrison 14Pentium III Xeonz improved cache11/29/2005 CS433 Luddy Harrison 15Pentium 4 (2000)z return to Arabic numeralsz NetBurst microarchitecturez SSE2 and SSE311/29/2005 CS433 Luddy Harrison 16Pentium 4 Supporting Hyper-Threading Technology (2004)z marketing team abandons names in favor of entire sentencesz Hyper-Threading is Simultaneous MultiThreading11/29/2005 CS433 Luddy Harrison 17Intel Xeon (2001-2004)z internal revolt against long namez recycled portion of old name(s) prevailsz multiprocessor supportz Was this the first Hyper-Threading IA32?11/29/2005 CS433 Luddy Harrison 18Intel Pentium M (2003)z The M is not a Roman Numeralz not “Pentium 1000”z refers to “Mobile”z low-powerz integrated wireless support11/29/2005 CS433 Luddy Harrison 1911/29/2005 CS433 Luddy Harrison 2011/29/2005 CS433 Luddy Harrison 2111/29/2005 CS433 Luddy Harrison 22NetBurst MicroArchitecture (Pentium 4)z deep branch predictionz dynamic dataflow analysisz instructions translated into a risc-like formz these in turn are subject to out-of-order executionz speculative executionz up to 126 instructions in flightz up to 48 loads and 24 stores in pipelinez advanced branch predictorz 4K branch target bufferz execution trace cache stores decoded instructionsz straightens code on the fly!z 8-way L2 cachez 64-byte cache line sizez external bus capable of 6.4Gbytes per second11/29/2005 CS433 Luddy Harrison 2311/29/2005 CS433 Luddy Harrison 24Front-End Pipelinez Prefetchz Fetch (on prefetch fail)z Decode into micro-operationsz Generate microcode from complex operationsz Delivers decoded instructions from execution trace cachez Branch prediction11/29/2005 CS433 Luddy Harrison 2511/29/2005 CS433 Luddy Harrison 26Instruction LayoutSee The Intel Manuals for Details11/29/2005 CS433 Luddy Harrison 27IA32 Instruction Format11/29/2005 CS433 Luddy Harrison 28What can you say about writing an optimizing compiler for IA32?11/29/2005 CS433 Luddy Harrison 29Registers11/29/2005 CS433 Luddy Harrison 30User-Visible Architectural State11/29/2005 CS433 Luddy Harrison 3111/29/2005 CS433 Luddy Harrison 32Special Register Purposes11/29/2005 CS433 Luddy Harrison 33Overlaid Registers11/29/2005 CS433 Luddy Harrison 34EFLAGS11/29/2005 CS433 Luddy Harrison 35System Status in EFLAGS11/29/2005 CS433 Luddy Harrison 36Data Types11/29/2005 CS433 Luddy Harrison 37Fundamental Data Types11/29/2005 CS433 Luddy Harrison 3811/29/2005 CS433 Luddy Harrison 39Floating Point Types11/29/2005 CS433 Luddy Harrison 4011/29/2005 CS433 Luddy Harrison 41IEEE 754 and IA32z Kahan et al formulated the proper working of floating point hardware in a documented standard known as IEEE 754z The x86 was designed to do all “scratch”calculations using a small floating point stackz the entries on the stack are 80-bit extended precision numbersz Unfortunately, this does not correspond well to the semantics of C11/29/2005 CS433 Luddy Harrison 42Example of Semantic Difference Between Natural x86 Execution and C Semanticsdouble A, B, C, D, E, F, G;// set B=D=F and C=E=G and let B*C be very close to 0 in// extended precision, but exactly 0 in double precision....// suppose we use the x86 FP stack to do this RHS:A = B*C + D*E - F*G; // this yields zero in double but non-zero// in extended precision...assert (A == 0.0);11/29/2005 CS433 Luddy Harrison 43Operating on


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