CS433: Computer System OrganizationOverviewIntroductionSystem UsesWireless Base StationWireless Base StationBasestation with Specialized PartsTigerSHARC replaces many partsSystem Uses SummaryCore Block DiagramCoreComputation Block Block DiagramComputation BlockComputation BlockISA SummaryVector AdditionX-side vector ops (2x32)X-side vector ops (4x16)Y-side vector opsY-side vector ops (4x16)XY vector ops (4x16 X&Y)ISA Summary - RegistersISA Summary – Assembly FormatISA Summary - PredicatesISA Summary - ALUISA Summary - ALUISA Summary - MultiplierISA Summary – CLU and ShifterISA Summary - IALUISA Summary - SequencerInstruction EncodingInstruction Encoding (Compute Block)Application UsesFIR FilterFIR FilterFIR Filter - OverallFIR Filter – some detailsFIR Filter Loop Detail – Half UnrollFIR Filter HighlightsTigerSHARC PipelinePipeline - NotesTiming – Result Use ConstraintsTiming – Result UseTiming - BranchesMemoryMemory Block DetailMemory Block DetailBlock DiagramPhysical Pin LayoutPinout DescriptionPinout DescriptionMechanicalMechanical ConsiderationsMechanical ConsiderationsMechanical ConsiderationsThermal NoteConclusionsCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 1CS433: Computer System OrganizationLuddy HarrisonAnalog Devices Incorporated TigerSHARC®CS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 2Overviewz The TigerSHARC is a very big chipz Quite complicatedz Also very interestingz We will use it to study several staticparallelism mechanisms:z Vector operationsz VLIW / SIMD executionz The TS201 manuals (HW and SW) are on the web site (under Processor Case Studies)CS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 3Introductionz Digital Signal Processor (DSP) by Analog Devices Inc.z System-on-chip designz RAM on chipz DMA controller on chipz SDRAM controller on chipz “Static Superscalar” (VLIW)z Hardware will issue things in parallel if told toz But it examines dependencies, and has no alignment requirementsz 4-way issuez SIMD (single instruction multiple data) capablez Very high throughputCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 4System Usesz 3G cellular/wireless infrastructurez Libraries to deal with physical-layer processing available for licensez Software-defined radiosz Image processingz Embedded applicationsz Use anywhere for high throughput math, with low power and costz Intended to replace ASICs and FPGAsCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 5Wireless Base Stationz Consider a wireless base stationz Receives analog radio signals at some set of frequenciesz Mustz Tune proper frequenciesz Turn the analog signal into digital symbolsz Deal with error detection/correctionz Decompress audio streamz Retransmit on land-line connectionz Does the reverse to send to cell phonesCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 6Wireless Base Stationz TS can doz Frequency filteringz Physical layer decodingz Error detect/correctz Entropy (de)codingz (Inverse) frequency transformz TS can not doz Physical layer interfacez D/Az A/DReplaces ASICs and/or passive electrical componentsCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 7Basestation with Specialized PartsCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 8TigerSHARC replaces many partsCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 9System Uses Summaryz One or a few TigerSHARCs can replace multiple ASICs or other partsz Increases flexibilityz Since the control is software, it is easy to upgrade to support new standards, new functionality, etc.z Reduces costz Can use a low-cost mass-produced part rather than an ASICz Easier to design than an ASIC or an FPGAz Flexibility (see above) allows same hardware design to be used for multiple purposesCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 10Core Block DiagramCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 11Corez Two I-ALUs, J and Kz Do integer arithmetic, moves, and load/storesz Called “Data Address Generators” in original SHARCz Two computation blocks, X and Yz Do ALU-type thingsz 4 bussesz J/K for dataz I for instructionsz S for outside worldz Internal memoryz On-die DRAM memory (24 Mbits)z Also has buffers/cachez Program sequencerz Instruction fetch, branch prediction, BTB, controlz System on chip interfacez Connects to main external bus, SRAM and DRAM controllers, link ports, JTAG port, etc.CS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 12Computation Block Block DiagramCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 13Computation Blockz Four functional unitsz ALUz Does arithmetic, logic, and packed data manipulationz Multiplierz Does multiply, multiply-accumulate, and complex numbersz Shifterz Does shifts, rotates, and bit-field manipulationsz CLUz Communications logic unitz Nifty things for communications and codingz Can use two of them every cycleCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 14Computation Blockz Data Alignment Bufferz Helps align unaligned accesses to circular buffersz Register filez 32 registers, 32 bits eachz Memory mappedz Functional units can operate on “packed” dataz Treat a 32 or 64 bit wide chunk of data as many 16 or 8 bit sub-chunksz Used for SIMD – single instruction multiple dataCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 15ISA Summaryz Has a lot of complex operations and features to support any sort of signal processing possiblez 250 pages for the ISA—this only summarizesz General featuresz Two kinds of SIMDz Can use packed data, ORz X unit and Y unit can do same thing on their own registersz Issue 4 instructions at a timez Can issue 1 to each IALU, 2 to each compute block E.g. use the J and K IALU, and issue a SIMD add to X and Y, and a SIMD multiple to X and Y Cannot use exact same functional unit twice (i.e. two X-unit adds)CS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 16Vector AdditionCS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 17X-side vector ops (2x32)+=XR0:1XR2:3XR4:5XR4:5 = R0:1 + R2:3CS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 18X-side vector ops (4x16)+=XR0:1XR2:3XR4:5XSR4:5 = R0:1 + R2:3CS 433 Prof. Luddy Harrison Copyright 2005 University of Illinois 19Y-side vector ops+=YR0:1YR2:3YR4:5YR4:5 = R0:1 + R2:3CS 433 Prof. Luddy Harrison Copyright 2005