U of I CS 433 - A Few Words on Endianness Pipelining

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CS433: Computer System OrganizationA Few Words On Endiannesslittle-endianbig-endianEndiannessAn Abstract PipelineTime on the Horizontal AxisPerformance of a PipelineClassic 5-Stage PipelineStage 1: IF (Instruction Fetch)Stage 2: ID (Instruction Decode / Register Fetch)Stage 3: EX (Execution / Effective Address)Stage 4: MEM (Memory Access)Stage 5: WB (Write Back)Classic Five-Stage PipeEdge-Triggered Latches are Used to Catch The Output of Each StageEdge-Triggered LatchInstruction Sets and HazardsHazardsSources of DelayDelays Are ConditionalDelays Due to FeedbackAbstract Pipeline with No Feedback0 Stage FeedbackSame-Stage Feedback1 Stage Feedback1-Cycle Delay due to Feedback2 Stage Feedback2-Cycle Delay due to FeedbackMultiple 0 Stage Feedback LoopsMultiple Same-Stage Feedback LoopsMultiple 1 Stage Feedback LoopsMultiple Sources of 1-Cycle DelayResource Sharing Across Pipe StagesDelays Induced by Resource ConflictResource ConflictRegister-Based DependenceMemory-Based Dependence in a non-Load/Store MachineRegister-Based DependenceTechniques for Keeping the Pipeline FullTechniques for Reducing Length of DelayRegister ForwardingStore ForwardingReplicating Shared ResourcesCombining StagesEnforcement of DelaysFilling Delay SlotsAnulling an InstructionFilling Conditional Branch Delay SlotsUnconditional Delay Slot FillingAnulled If Branch TakenAnulled If Branch Not TakenAny Kind of Delay Slot Can Be Filled Using Instruction SchedulingNOP-filling When Static Scheduling is RequiredResource ConflictsStatic and Dynamic Mechanisms for Reducing Impact of Pipeline FeedbackStructural Hazard: Conflict for Access to Single-Ported MemoryData Hazard: Inter-Instrution Flow DependencesRegister ForwardingForwarding Load Result to Store InstructionWe Can’t Forward BackwardsScheduling Branch Delay SlotsSimple Processor Before PipeliningSimple Processor With Latches InsertedRegister Forwarding Requires Additional ALU Inputs & PathsReducing Branch LatencyUnpipelined Multi-Cycle OperationsPipelined MultiCycle OperationsStalls Per Insn in SPEC INTStalls Per Insn in SPEC FPR4000 Pipeline (8 Stages)R4000 Pipe Stages2-Cycle Load DelayBranch delay is 3 cyclesR4000 Stall TypesPipeline CPI for SPEC92 Assuming Perfect CacheMIPS Processor with Scoreboard9/13/2005 CS433 Luddy Harrison 1CS433: Computer System OrganizationLuddy HarrisonA Few Words on EndiannessPipelining9/13/2005 CS433 Luddy Harrison 2A Few Words On Endiannessz Source of much confusionz Actually very simple9/13/2005 CS433 Luddy Harrison 3little-endianz If 32-bit number is ABCD, then it is stored in memory asz xxx00: Dz xxx01: Cz xxx02: Bz xxx03: Az Little-endian = least significant byte stored at lowest addressz This has nothing whatsoever to do with the format of data in registers!z The position of the MSB and LSB in a register is fixed and is never in question.9/13/2005 CS433 Luddy Harrison 4big-endianz If 32-bit number is ABCD, then it is stored in memory asz xxx00: Az xxx01: Bz xxx02: Cz xxx03: Dz Big-endian = most significant byte stored at lowest addressz This has nothing whatsoever to do with the format of data in registers!z The position of the MSB and LSB in a register is fixed and is never in question.9/13/2005 CS433 Luddy Harrison 5Endiannessz Endianness is concerned with the addresses of the individual bytes that make up a multi-byte datumz Endianness has no effect on the storage of an array of bytes (chars)z Endianness has no effect on the representation of data in registersz It becomes visible only when:z K-byte data is accessed in units of fewer than K bytesz E.g., 4-byte integers read from memory as 2-byte shortsz Data stored according to a little-endian convention is loaded according to a big-endian convention, or vice-versa.9/13/2005 CS433 Luddy Harrison 6An Abstract PipelineA B C D E F I1 I2 I1 I3 I2 I1 I4 I3 I2 I1 I5 I4 I3 I2 I1 I6 I5 I4 I3 I2 I1 I6 I5 I4 I3 I2 I6 I5 I4 I3 I6 I5 I4 I6 I5 I6stagesCycle 1:Cycle 2:Cycle 3:Cycle 4:Cycle 5:Cycle 6:Cycle 7:Cycle 8:Cycle 9:Cycle 10:Cycle 11:timePipeline is full•The pipeline has six stages.•It can hold six in-flight instructions at once•It takes six cycles to fill it up.•It takes six cycles to drain it.•It takes six cycles to perform one instruction•It completes one instruction per cycle (at most)•This is independent of the number of stages!9/13/2005 CS433 Luddy Harrison 7Time on the Horizontal AxisA B C D E FA B C D E FA B C D E FA B C D E FA B C D E FA B C D E FThis is how CA:AQA displays a pipeline over time.9/13/2005 CS433 Luddy Harrison 8Performance of a Pipelinestagespipenumbertimedunpipelinetimepipelined____ ≥istagesitimestagetimepipelined _max_∈=These equations describe the time per output of the pipeline. The latency for a single item to pass through the pipeline is simply the sum of the individual stage times.In practice, all stages take the same amount of time, which is simply the clock period (in the case of synchronous pipelines anyway).9/13/2005 CS433 Luddy Harrison 9Classic 5-Stage Pipelinez IF (Instruction Fetch)z ID (Instruction Decode / Register Fetch)z EX (Execute / Effective Address Calculation)z MEM (Memory Access)z WR (Write Back)9/13/2005 CS433 Luddy Harrison 10Stage 1: IF (Instruction Fetch)z Address instruction memory using PCz PC = PC + k9/13/2005 CS433 Luddy Harrison 11Stage 2: ID (Instruction Decode / Register Fetch)z Decode the instructionz Produce control signalsz Fetch source registersz Compare them unconditionally in case insn is conditional branchz Sign-extend the immediate fieldz Compute PC + signextend(offset)z We are ready to performPC = PC + signextend(offset)if the condition


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