CS433: Computer System OrganizationAdditional Slides and DocumentsMIPS ISAARM Family OverviewARM EvolutionARMv3ARMv4ARMv5ARMv6Some ARM ImplementationsARM DSP Extensions (E)ARMv6 SIMD Extensions (Complex Multiply)ARMv6 Endianness Support via E bitARMv6 Byte Reverse InsnsARM9E Datapath with DSP Extensions HighlightedARM11 MicroArchitectureCS433: Computer System OrganizationLuddy HarrisonMIPS and ARM Instruction SetsAdditional Slides and Documentsz CA:AQA Appendix Cz ARM V1 Instruction Set (PPT Presentation)z ARM ISA v2.1 Reference Cardz Thumb ISA v2.1 Reference Cardz ARMv6 Architecturez ARM11 MicroArchitecturez Intel XScale presentation on my web siteGo to “Processor Case Studies” page on course web site.MIPS ISAARM Family Overviewz Architecture Versionsz ARM V3, V4, V5, V6z Called “architecture” in their literature, this is the programmer’s view of the machinez The externally visible architecturez It is primarily a matter of Instruction Set Architecturez Implementationsz ARM7, ARM9, ARM10, ARM11z With letter extensions – to be explained shortlyz Called “cores” in their literatureARM EvolutionARMv3z V3 introduced 32-bit addressing, and architecture variants:z T – Thumb state: 16-bit instruction execution.z M – long multiply support (32 × 32 → 64 or 32 ×32 + 64 → 64).z These features became standard in architecture V4 and beyond.ARMv4z Halfword Load and StoreARMv5z Improved ARM and Thumb interworkingz count leading-zeroes (CLZ) instructionz architecture variants:z E – enhanced DSP instructions including saturated arithmetic operations and 16-bit multiply operationsz J – support for new Java state, offering hardware and optimized software acceleration of bytecodeexecution.ARMv6z All of T, M, E, and J extensionsz 60+ SIMD instructionsz Improved Mixed-Endian Supportz E.g, Little-Endian OS + Bit-Endian Dataz Improved Unaligned Data Supportz Important in DSP applicationsz Improved Performance in Exception and Interrupt Handlingz Four New Status Flags:z GE[3:0] bitsz SIMD status bits - greater than or equal to for each 8/16-bit slicez • E-bitz Indicates the current load/store endiansetting of the corez Can be set/cleared with the SETEND instructionz • A-bitz Indicates if imprecise data abort exceptions are maskedz Improved Virtual Memory Supportz Phyically Tagged Cache Linesz Improved Multiprocessor Supportz Memory Coherencez Semaphore Instructions28 Jan 2005 Copyright ARM Ltd. 2002Some ARM ImplementationsARM DSP Extensions (E)ARMv6 SIMD Extensions(Complex Multiply)ARMv6 Endianness Support via E bitARMv6 Byte Reverse InsnsARM9E Datapath with DSP Extensions Highlighted28 Jan 2005 Copyright ARM Ltd. 2002ARM11
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