Ch3-fig02.epsFig3_5.pdfSheet1Ch3-fig29.epsFig3_32.pdfSheet2State Wait Unit Action / BookkeepingCommentsIssueFP Op Station r emptyif (RegisterStat[rs].Qi != 0) RS[r].Qj = RegisterStat[rs].Qielse RS[r].Vj = Regs[rs] RS[r].Qj = 0if (RegisterStat[rt].Qi != 0) RS[r].Qk = RegisterStat[rt].Qielse RS[r].Vk = Regs[rt] RS[r].Qk = 0RS[r].Busy = trueRegisterStat[rd].Qi = rfind operand 1find operand 2mark resv station r busymark desination reg as being computed by resv station rLoad/Store Buffer r emptyif (RegisterStat[rs].Qi != 0) RS[r].Qj = RegisterStat[rs].Qielse RS[r].Vj = Regs[rs] RS[r].Qj = 0RS[r].Busy = trueRS[r].A = immfind operand 1 (address reg)mark buffer r busyrecord offset in A field of rLoad only RegisterStat[r].Qi = rmark destination reg as being computed by buffer rStore onlyif (RegisterStat[rt].Qi != 0) RS[r].Qk = RegisterStat[rt].Qielse RS[r].Vk = Regs[rt] RS[r].Qk = 0find operand 2 (store data)ExecuteFP OpRS[r].Qj = 0 and RS[r].Qk = 0Compute result (Vj OP Vk)wait until operands are readycompute result from operands in reservation station Vj and VkLoad/Store step 1RS[r].Qj = 0 andr is head of load/store queueRS[r].A = RS[r].Vj + RS[r].Acompute effective from base address reg + offsetLoad step 2Load step 1 completeresult = Mem[RS[r].A]press effective address onto address bus & wait for data to come back from memoryWrite resultFP Op, LoadExecution phase of instruction r complete and CDB available∀x∈regs, if (RegisterStat[x].Qi = r) Regs[x] = result RegisterStat[x].Qi = 0∀x∈resv, if (RS[x].Qj = r) RS[x].Vj = result RS[x].Qj = 0∀x∈resv, if (RS[x].Qk = r) RS[x].Vk = result RS[x].Qk = 0RS[r].Busy = noWait for execution to finish and for CDB to be free! Note the waiting for CDBfor all registers x, if x is waiting to be stored by instruction r, then store the result into reg x and mark the register as not waiting for r.for all resv stations x, if Qj or Qk of the reservation station is waiting for the result of r, then store the result into Qj or Qk and mark the reservation station as not waiting for r.Note that nothing from reservation station r is read here! We could have released r earlier (at Execute), provided that results are enqueued at output of FP unit / load unit, along with identity (r) of reservation station producting the result.Store onlyExecution phase of instruction r complete and RS[r].Qk = 0Mem[RS[r].A] = RS[r].VkRS[r].Busy = falsewait for execution to finish and for store data to be availableState Wait UnitAction / BookkeepingCommentsIssueall instructionsStation r and ROB b emptyif (RegisterStat[rs].Busy) h = RegisterStat[rs].Reorder if (ROB[h].Ready) RS[r].Vj = ROB[h].Value RS[r].Qj = 0 else RS[r].Qj = helse RS[r].Vj = Regs[rs] RS[r].Qj = 0RS[r].Busy = trueRS[r].Dest = bROB[b].Instruction = opcodeROB[b].Dest = rdROB[b].Ready = falseif operand 1 (rs) is being computed by an in-flight instruction, then find out what ROB it is in (call this h). If h is ready, then get the value of rs from ROB[h].Value. Otherwise mark operand 1 as waiting on h by setting Qj to h.If operand 1 (rs) is not being computed by an in-flight instruction, then simply get rs from Regs and mark operand 1 as not waiting by setting Qj to 0.Mark the reservation station r as busy and its destination as reorder buffer b.Record the opcode and destination reg (rd) in ROB[b].FP OPs and Storesif (RegisterStat[rt].Busy) h = RegisterStat[rt].Reorder if (ROB[h].Ready) RS[r].Vk = ROB[h].Value RS[r].Qk = 0 else RS[r].Qk = helse RS[r].Vk = Regs[rs] RS[r].Qk = 0if operand 2 (rt) is being computed by an in-flight instruction, then find out what ROB it is in (call this h). If h is ready, then get the value of rt from ROB[h].Value. Otherwise mark operand 2 as waiting on h by setting Qk to h.If operand 2 (rt) is not being computed by an in-flight instruction, then simply get rt from Regs and mark operand 2 as not waiting by setting Qk to 0.FP OPsRegisterStat[rd].Qi = bRegisterStat[rd].Busy = trueROB[b].Dest = rdmark destination reg as being computed by reorder buffer bLoadsRS[r].A = immRegisterStat[rt].Qi = bRegisterStat[rt].Busy = trueROB[b].Dest = rtStores RS[r].A = immExecuteFP OpRS[r].Qj = 0andRS[r].Qk = 0Compute result (Vj OP Vk)wait until operands are readycompute result from operands in reservation station Vj and VkLoad step 1RS[r].Qj = 0 andthere are no stores ahead of r in the queueRS[r].A = RS[r].Vj + RS[r].Acompute effective from base address reg + offsetLoad step 2Load step 1 and all stores earlier in ROB are independent of this loadresult = Mem[RS[r].A]press effective address onto address bus & wait for data to come back from memoryStoreRS[r].Qj = 0andstore is at head of queueROB[h].Address = RS[v].Vj + RS[r].Ahold effective address in reorder buffer h. Note that h is the ROB for instruction r (RS[r].Dest).Write resultall but storeexecution done for instruction r and CDB availableb = RS[r].ReorderRS[r].Busy = false∀x, if RS[s].Qj=b RS[x].Vj = result RS[x].Qj = 0∀x, if RS[s].Qk=b RS[x].Vk = result RS[x].Qk = 0ROB[b].Value = resultROB[b].Ready = truelet b be reorder buffer for this insn.Mark RS[r] as no longer needed.forall reservation stations x, if operand 1 or 2 of x is wating for b, then store the result into operand 1 or 2 of reservation station x and mark it as not wating.Store the result into the reorder buffer b, and mark b as ready.StoreExecution phase of instruction r complete and RS[r].Qk = 0ROB[h].Value = RS[r].Vkmove store data from reservation station r into reorder buffer h. h is the ROB for instruction r (RS[r].Dest).CommitallInstruction is at the head of the ROB (entry h) and ROB[h].Ready = trued = ROB[h].Destif (ROB[h].Instruction = Branch) if (branch is mispredicted) clear ROB[h] clear RegisterStat fetch branch destelse if (ROB[h].Instruction = Store) Mem[ROB[h].Address] = ROB[h].Valueelse Regs[d] = ROB[h].ValueROB[h].Busy = falseif (RegisterStat[d].Qi = h) RegisterStat[d].Busy = nolet d be the register destination, if anyif mispredicted branch, clear ROB[h] and RegisterStat and proceed from branch destif store, deliver Value to memory Addressotherwise, write result from ROB[h].Value into Regs[d].mark ROB[h] as free.if destination register is still waiting for this ROB, then mark the destination register as not